Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.84 100.00 89.19 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.58 100.00 90.30 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.58 100.00 90.30 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT34,T89
110Not Covered
111CoveredT2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT31,T35,T30
101CoveredT2,T3,T9
110Not Covered
111CoveredT2,T3,T9

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 386610684 1042005 0 0
DepthKnown_A 387378572 387047350 0 0
RvalidKnown_A 387378572 387047350 0 0
WreadyKnown_A 387378572 387047350 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 386977198 1136348 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 386610684 1042005 0 0
T2 3996 1451 0 0
T3 7076 2656 0 0
T4 0 291 0 0
T7 0 35 0 0
T9 8424 6357 0 0
T10 4642 858 0 0
T17 0 10647 0 0
T18 5810 0 0 0
T19 3698 1562 0 0
T20 1276 0 0 0
T21 7550 0 0 0
T22 4244 0 0 0
T41 0 1756 0 0
T60 0 2441 0 0
T70 6538 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387378572 387047350 0 0
T1 2774 2636 0 0
T2 3996 3832 0 0
T3 7076 6942 0 0
T9 8424 8250 0 0
T10 4642 4454 0 0
T18 5810 5684 0 0
T19 3698 3518 0 0
T20 1276 1112 0 0
T21 7550 7352 0 0
T22 4244 4054 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387378572 387047350 0 0
T1 2774 2636 0 0
T2 3996 3832 0 0
T3 7076 6942 0 0
T9 8424 8250 0 0
T10 4642 4454 0 0
T18 5810 5684 0 0
T19 3698 3518 0 0
T20 1276 1112 0 0
T21 7550 7352 0 0
T22 4244 4054 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387378572 387047350 0 0
T1 2774 2636 0 0
T2 3996 3832 0 0
T3 7076 6942 0 0
T9 8424 8250 0 0
T10 4642 4454 0 0
T18 5810 5684 0 0
T19 3698 3518 0 0
T20 1276 1112 0 0
T21 7550 7352 0 0
T22 4244 4054 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 386977198 1136348 0 0
T2 3996 1451 0 0
T3 7076 2656 0 0
T4 0 1283 0 0
T6 0 278 0 0
T9 8424 6357 0 0
T10 4642 858 0 0
T13 0 313 0 0
T17 0 10647 0 0
T18 5810 0 0 0
T19 3698 1562 0 0
T20 1276 0 0 0
T21 7550 0 0 0
T22 4244 0 0 0
T60 0 2441 0 0
T70 6538 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT31,T35,T90
101CoveredT2,T3,T9
110Not Covered
111CoveredT2,T3,T9

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 193305342 525937 0 0
DepthKnown_A 193689286 193523675 0 0
RvalidKnown_A 193689286 193523675 0 0
WreadyKnown_A 193689286 193523675 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 193488599 573208 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193305342 525937 0 0
T2 1998 733 0 0
T3 3538 1353 0 0
T4 0 161 0 0
T7 0 30 0 0
T9 4212 3183 0 0
T10 2321 486 0 0
T17 0 5337 0 0
T18 2905 0 0 0
T19 1849 821 0 0
T20 638 0 0 0
T21 3775 0 0 0
T22 2122 0 0 0
T41 0 961 0 0
T60 0 1295 0 0
T70 3269 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 193488599 573208 0 0
T2 1998 733 0 0
T3 3538 1353 0 0
T4 0 658 0 0
T6 0 133 0 0
T9 4212 3183 0 0
T10 2321 486 0 0
T13 0 151 0 0
T17 0 5337 0 0
T18 2905 0 0 0
T19 1849 821 0 0
T20 638 0 0 0
T21 3775 0 0 0
T22 2122 0 0 0
T60 0 1295 0 0
T70 3269 0 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT43,T82,T91
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT34,T89
110Not Covered
111CoveredT2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT30,T92,T93
101CoveredT2,T3,T9
110Not Covered
111CoveredT2,T3,T9

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 193305342 516068 0 0
DepthKnown_A 193689286 193523675 0 0
RvalidKnown_A 193689286 193523675 0 0
WreadyKnown_A 193689286 193523675 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 193488599 563140 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193305342 516068 0 0
T2 1998 718 0 0
T3 3538 1303 0 0
T4 0 130 0 0
T7 0 5 0 0
T9 4212 3174 0 0
T10 2321 372 0 0
T17 0 5310 0 0
T18 2905 0 0 0
T19 1849 741 0 0
T20 638 0 0 0
T21 3775 0 0 0
T22 2122 0 0 0
T41 0 795 0 0
T60 0 1146 0 0
T70 3269 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 193689286 193523675 0 0
T1 1387 1318 0 0
T2 1998 1916 0 0
T3 3538 3471 0 0
T9 4212 4125 0 0
T10 2321 2227 0 0
T18 2905 2842 0 0
T19 1849 1759 0 0
T20 638 556 0 0
T21 3775 3676 0 0
T22 2122 2027 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 193488599 563140 0 0
T2 1998 718 0 0
T3 3538 1303 0 0
T4 0 625 0 0
T6 0 145 0 0
T9 4212 3174 0 0
T10 2321 372 0 0
T13 0 162 0 0
T17 0 5310 0 0
T18 2905 0 0 0
T19 1849 741 0 0
T20 638 0 0 0
T21 3775 0 0 0
T22 2122 0 0 0
T60 0 1146 0 0
T70 3269 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%