Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	708475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5920485

1

T1

5

T2

30

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1739176	1			T1	1		T2	92		T3	45
values[0x0]	2260709	1			T1	3		T2	12		T3	5
values[0x1]	2629075	1			T1	1		T2	17		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	345598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6283362

1

T1

5

T2

56

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25346	1			T40	797		T46	2		T41	461
valid_sources[0x01]	27375	1			T40	647		T65	1		T41	483
valid_sources[0x02]	26320	1			T40	851		T46	1		T41	473
valid_sources[0x03]	24783	1			T25	2		T40	936		T41	464
valid_sources[0x04]	25473	1			T3	4		T4	1		T40	595
valid_sources[0x05]	25594	1			T40	857		T46	3		T41	468
valid_sources[0x06]	24935	1			T3	3		T14	6		T40	826
valid_sources[0x07]	25683	1			T25	1		T43	3		T40	773
valid_sources[0x08]	26822	1			T40	862		T65	2		T46	1
valid_sources[0x09]	28259	1			T40	714		T41	465		T42	26
valid_sources[0x0a]	26679	1			T40	960		T41	480		T42	54
valid_sources[0x0b]	26950	1			T40	876		T41	445		T42	58
valid_sources[0x0c]	24977	1			T8	5		T40	881		T46	1
valid_sources[0x0d]	26231	1			T3	1		T47	1		T40	818
valid_sources[0x0e]	25154	1			T43	4		T40	792		T65	1
valid_sources[0x0f]	25724	1			T40	747		T65	2		T46	1
valid_sources[0x10]	24791	1			T26	1		T40	751		T41	445
valid_sources[0x11]	26117	1			T43	3		T40	716		T65	3
valid_sources[0x12]	26523	1			T43	6		T40	665		T65	2
valid_sources[0x13]	26273	1			T3	2		T4	1		T43	3
valid_sources[0x14]	25374	1			T40	829		T41	469		T42	61
valid_sources[0x15]	25793	1			T40	805		T41	466		T42	47
valid_sources[0x16]	25547	1			T47	1		T40	725		T65	1
valid_sources[0x17]	24736	1			T47	1		T40	755		T65	1
valid_sources[0x18]	26206	1			T40	837		T41	453		T42	48
valid_sources[0x19]	26127	1			T3	1		T40	705		T46	2
valid_sources[0x1a]	25169	1			T40	828		T46	2		T41	486
valid_sources[0x1b]	25666	1			T4	1		T40	736		T45	1
valid_sources[0x1c]	25713	1			T40	744		T41	464		T42	45
valid_sources[0x1d]	26499	1			T43	5		T40	819		T41	516
valid_sources[0x1e]	26163	1			T40	798		T65	1		T41	467
valid_sources[0x1f]	25816	1			T43	3		T40	737		T46	2
valid_sources[0x20]	25146	1			T4	1		T40	744		T41	462
valid_sources[0x21]	25079	1			T40	834		T41	413		T42	46
valid_sources[0x22]	24892	1			T8	1		T40	881		T41	495
valid_sources[0x23]	27777	1			T40	809		T41	490		T42	46
valid_sources[0x24]	26868	1			T47	2		T40	824		T41	472
valid_sources[0x25]	26412	1			T3	1		T40	727		T65	1
valid_sources[0x26]	25265	1			T2	121		T4	1		T40	772
valid_sources[0x27]	25775	1			T4	2		T40	785		T41	492
valid_sources[0x28]	25579	1			T8	4		T43	3		T40	730
valid_sources[0x29]	24341	1			T3	2		T40	783		T46	1
valid_sources[0x2a]	25962	1			T43	14		T40	736		T41	512
valid_sources[0x2b]	26045	1			T47	1		T40	679		T41	486
valid_sources[0x2c]	25713	1			T40	818		T49	89		T41	470
valid_sources[0x2d]	24996	1			T40	793		T65	2		T41	472
valid_sources[0x2e]	26782	1			T40	913		T41	458		T42	29
valid_sources[0x2f]	25820	1			T4	1		T40	901		T41	433
valid_sources[0x30]	26447	1			T47	1		T40	810		T46	1
valid_sources[0x31]	25686	1			T40	732		T46	1		T41	462
valid_sources[0x32]	25817	1			T40	867		T41	494		T50	1
valid_sources[0x33]	23527	1			T40	781		T46	1		T41	444
valid_sources[0x34]	26533	1			T40	829		T46	1		T41	464
valid_sources[0x35]	24626	1			T4	1		T43	2		T40	747
valid_sources[0x36]	25914	1			T4	1		T40	766		T46	1
valid_sources[0x37]	25671	1			T40	688		T65	1		T46	4
valid_sources[0x38]	27669	1			T40	847		T46	1		T41	456
valid_sources[0x39]	25892	1			T40	900		T46	1		T41	456
valid_sources[0x3a]	25782	1			T43	4		T40	774		T46	1
valid_sources[0x3b]	24959	1			T40	862		T41	450		T42	44
valid_sources[0x3c]	26719	1			T47	4		T40	863		T65	1
valid_sources[0x3d]	25575	1			T4	1		T8	2		T14	1
valid_sources[0x3e]	24051	1			T4	1		T47	1		T40	883
valid_sources[0x3f]	27833	1			T40	853		T65	1		T46	1
valid_sources[0x40]	27092	1			T40	999		T65	1		T46	1
valid_sources[0x41]	26986	1			T40	812		T65	2		T41	483
valid_sources[0x42]	24725	1			T40	735		T41	493		T42	64
valid_sources[0x43]	25366	1			T40	782		T41	530		T42	55
valid_sources[0x44]	25058	1			T40	803		T41	461		T42	31
valid_sources[0x45]	27774	1			T43	7		T40	772		T65	1
valid_sources[0x46]	25587	1			T40	771		T46	1		T41	489
valid_sources[0x47]	25487	1			T26	1		T40	812		T41	478
valid_sources[0x48]	26101	1			T4	1		T43	7		T40	790
valid_sources[0x49]	26672	1			T40	742		T65	1		T46	2
valid_sources[0x4a]	25524	1			T3	2		T43	10		T40	704
valid_sources[0x4b]	24634	1			T24	1		T43	8		T47	1
valid_sources[0x4c]	26428	1			T40	819		T46	1		T41	470
valid_sources[0x4d]	25316	1			T4	1		T40	770		T41	449
valid_sources[0x4e]	24090	1			T40	701		T41	507		T42	35
valid_sources[0x4f]	25749	1			T47	1		T40	891		T41	440
valid_sources[0x50]	24039	1			T3	2		T4	1		T40	746
valid_sources[0x51]	26620	1			T43	4		T40	858		T65	2
valid_sources[0x52]	25148	1			T40	755		T41	449		T42	38
valid_sources[0x53]	25589	1			T40	866		T65	1		T46	1
valid_sources[0x54]	23731	1			T40	911		T41	495		T42	45
valid_sources[0x55]	26846	1			T43	8		T40	726		T41	465
valid_sources[0x56]	29234	1			T40	793		T44	152		T41	471
valid_sources[0x57]	24623	1			T4	1		T40	724		T41	460
valid_sources[0x58]	26734	1			T40	756		T41	513		T42	48
valid_sources[0x59]	26768	1			T3	3		T43	15		T40	927
valid_sources[0x5a]	25416	1			T40	682		T65	1		T46	1
valid_sources[0x5b]	27172	1			T43	5		T40	790		T41	486
valid_sources[0x5c]	26746	1			T43	19		T47	4		T40	879
valid_sources[0x5d]	27775	1			T3	1		T40	756		T41	459
valid_sources[0x5e]	26719	1			T27	81		T40	825		T41	440
valid_sources[0x5f]	25909	1			T40	802		T65	1		T41	504
valid_sources[0x60]	25648	1			T40	964		T65	1		T41	512
valid_sources[0x61]	25679	1			T40	647		T65	2		T46	4
valid_sources[0x62]	26392	1			T40	792		T46	1		T41	440
valid_sources[0x63]	26565	1			T24	3		T40	864		T41	497
valid_sources[0x64]	25728	1			T40	775		T41	459		T50	1
valid_sources[0x65]	24446	1			T14	1		T40	726		T46	3
valid_sources[0x66]	26612	1			T43	3		T47	4		T40	703
valid_sources[0x67]	24328	1			T4	1		T43	12		T40	809
valid_sources[0x68]	26332	1			T40	730		T65	1		T41	475
valid_sources[0x69]	26457	1			T40	775		T41	442		T42	71
valid_sources[0x6a]	25070	1			T47	1		T40	766		T41	522
valid_sources[0x6b]	25003	1			T40	675		T41	492		T42	56
valid_sources[0x6c]	25299	1			T4	1		T8	3		T40	741
valid_sources[0x6d]	25873	1			T3	2		T47	1		T40	885
valid_sources[0x6e]	25703	1			T3	2		T43	2		T40	719
valid_sources[0x6f]	25998	1			T4	1		T40	799		T46	1
valid_sources[0x70]	27505	1			T43	4		T40	810		T65	1
valid_sources[0x71]	24900	1			T4	1		T40	745		T46	2
valid_sources[0x72]	26025	1			T8	1		T40	792		T41	466
valid_sources[0x73]	23949	1			T4	1		T40	838		T46	2
valid_sources[0x74]	25653	1			T1	5		T47	1		T40	953
valid_sources[0x75]	26586	1			T40	778		T65	1		T46	3
valid_sources[0x76]	25778	1			T3	2		T8	1		T43	1
valid_sources[0x77]	26484	1			T47	3		T40	761		T46	1
valid_sources[0x78]	26225	1			T40	710		T65	1		T41	483
valid_sources[0x79]	26016	1			T40	822		T41	481		T42	45
valid_sources[0x7a]	26124	1			T4	1		T8	2		T40	807
valid_sources[0x7b]	24762	1			T3	1		T40	719		T46	5
valid_sources[0x7c]	25498	1			T3	1		T8	1		T40	673
valid_sources[0x7d]	25611	1			T40	836		T46	2		T41	493
valid_sources[0x7e]	25515	1			T4	1		T47	1		T40	782
valid_sources[0x7f]	26317	1			T4	2		T8	9		T40	806
valid_sources[0x80]	25855	1			T24	21		T47	2		T40	934

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1490010

1

T1

1

T2

7

T3

3

values[0x0]

all_enables

biggest_size

2215457

1

T1

3

T2

9

T3

3

values[0x1]

all_enables

biggest_size

2215018

1

T1

1

T2

14

T3

1