Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2472	1			T8	1		T43	1		T47	2
non_zero_bins[1]	1689	1			T2	1		T27	1		T8	1
zero	7939	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	457	1			T27	1		T43	1		T40	11
uni	3372	1			T2	1		T24	1		T27	1
gen	3634	1			T1	1		T2	1		T3	1
res	760	1			T8	1		T47	1		T40	12
ins	3877	1			T1	2		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8222

1

T1

2

T2

3

T3

2

mubi_true

3878

1

T1

1

T2

1

T25

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

30

1

T9

1

T31

1

T32

1

pass

12070

1

T1

3

T2

4

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	115	1			T40	2		T83	1		T82	1
upd	non_zero_bins[0]	pass	mubi_true	109	1			T40	3		T41	2		T165	1
upd	non_zero_bins[1]	pass	mubi_false	62	1			T40	2		T41	1		T79	1
upd	non_zero_bins[1]	pass	mubi_true	75	1			T40	3		T79	1		T240	1
upd	zero	pass	mubi_false	51	1			T43	1		T40	1		T41	1
upd	zero	pass	mubi_true	45	1			T27	1		T42	1		T79	1
uni	zero	fail	mubi_false	8	1			T88	1		T158	1		T168	1
uni	zero	pass	mubi_false	2503	1			T2	1		T24	1		T27	1
uni	zero	pass	mubi_true	861	1			T40	25		T65	1		T41	9
gen	non_zero_bins[0]	pass	mubi_false	477	1			T47	1		T40	11		T49	1
gen	non_zero_bins[0]	pass	mubi_true	432	1			T43	1		T40	8		T41	4
gen	non_zero_bins[1]	pass	mubi_false	289	1			T27	1		T40	6		T44	1
gen	non_zero_bins[1]	pass	mubi_true	299	1			T40	5		T41	1		T42	3
gen	zero	fail	mubi_false	12	1			T9	1		T31	1		T32	1
gen	zero	pass	mubi_false	1722	1			T2	1		T3	1		T24	1
gen	zero	pass	mubi_true	403	1			T1	1		T25	1		T47	1
res	non_zero_bins[0]	pass	mubi_false	166	1			T40	2		T42	2		T13	2
res	non_zero_bins[0]	pass	mubi_true	186	1			T40	6		T44	1		T41	3
res	non_zero_bins[1]	pass	mubi_false	112	1			T47	1		T40	2		T41	1
res	non_zero_bins[1]	pass	mubi_true	138	1			T8	1		T40	1		T49	1
res	zero	fail	mubi_false	5	1			T171	1		T241	1		T242	1
res	zero	pass	mubi_false	70	1			T40	1		T41	1		T50	1
res	zero	pass	mubi_true	83	1			T41	1		T42	1		T78	1
ins	non_zero_bins[0]	pass	mubi_false	503	1			T8	1		T47	1		T40	13
ins	non_zero_bins[0]	pass	mubi_true	484	1			T40	10		T41	7		T50	1
ins	non_zero_bins[1]	pass	mubi_false	359	1			T2	1		T43	1		T40	12
ins	non_zero_bins[1]	pass	mubi_true	355	1			T40	9		T46	1		T41	3
ins	zero	fail	mubi_false	5	1			T146	1		T147	1		T148	1
ins	zero	pass	mubi_false	1763	1			T1	2		T3	1		T24	1
ins	zero	pass	mubi_true	408	1			T2	1		T25	1		T26	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded