Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T93,T94
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T35,T39
1	0	1	Covered	T3,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	448341208	980156	0	0
DepthKnown_A	449143118	448766318	0	0
RvalidKnown_A	449143118	448766318	0	0
WreadyKnown_A	449143118	448766318	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	448728180	1078292	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	448341208	980156	0	0
T5	530	183	0	0
T6	0	243	0	0
T8	3914	2220	0	0
T9	0	412	0	0
T13	0	1876	0	0
T14	276	0	0	0
T20	0	1213	0	0
T23	0	1523	0	0
T26	1696	0	0	0
T27	6436	0	0	0
T31	0	914	0	0
T32	0	708	0	0
T40	1186600	0	0	0
T43	7262	0	0	0
T44	7990	0	0	0
T45	2258	0	0	0
T47	3878	0	0	0
T95	0	599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449143118	448766318	0	0
T1	1508	1360	0	0
T2	8544	8440	0	0
T3	1808	1514	0	0
T4	1710	1456	0	0
T5	1610	1276	0	0
T8	3914	3788	0	0
T24	2736	2586	0	0
T25	2146	1984	0	0
T26	1696	1552	0	0
T27	6436	6252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449143118	448766318	0	0
T1	1508	1360	0	0
T2	8544	8440	0	0
T3	1808	1514	0	0
T4	1710	1456	0	0
T5	1610	1276	0	0
T8	3914	3788	0	0
T24	2736	2586	0	0
T25	2146	1984	0	0
T26	1696	1552	0	0
T27	6436	6252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449143118	448766318	0	0
T1	1508	1360	0	0
T2	8544	8440	0	0
T3	1808	1514	0	0
T4	1710	1456	0	0
T5	1610	1276	0	0
T8	3914	3788	0	0
T24	2736	2586	0	0
T25	2146	1984	0	0
T26	1696	1552	0	0
T27	6436	6252	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	448728180	1078292	0	0
T3	904	7	0	0
T4	855	0	0	0
T5	1610	721	0	0
T8	3914	2220	0	0
T9	0	412	0	0
T13	0	1876	0	0
T14	1370	220	0	0
T15	0	224	0	0
T20	0	622	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	1696	0	0	0
T27	6436	0	0	0
T31	0	914	0	0
T32	0	708	0	0
T40	593300	0	0	0
T43	7262	0	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T47	1939	0	0	0
T64	0	243	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T62,T96,T97
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T39,T98
1	0	1	Covered	T3,T5,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T13,T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	224170604	485124	0	0
DepthKnown_A	224571559	224383159	0	0
RvalidKnown_A	224571559	224383159	0	0
WreadyKnown_A	224571559	224383159	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	224364090	533933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224170604	485124	0	0
T5	265	61	0	0
T6	0	86	0	0
T8	1957	1100	0	0
T9	0	208	0	0
T13	0	906	0	0
T14	138	0	0	0
T20	0	591	0	0
T23	0	738	0	0
T26	848	0	0	0
T27	3218	0	0	0
T31	0	441	0	0
T32	0	360	0	0
T40	593300	0	0	0
T43	3631	0	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T47	1939	0	0	0
T95	0	294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	224364090	533933	0	0
T3	904	7	0	0
T4	855	0	0	0
T5	805	321	0	0
T8	1957	1100	0	0
T9	0	208	0	0
T13	0	906	0	0
T14	685	111	0	0
T15	0	113	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T31	0	441	0	0
T32	0	360	0	0
T43	3631	0	0	0
T64	0	124	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T8,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T93,T94
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T99
1	0	1	Covered	T5,T8,T14
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	224170604	495032	0	0
DepthKnown_A	224571559	224383159	0	0
RvalidKnown_A	224571559	224383159	0	0
WreadyKnown_A	224571559	224383159	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	224364090	544359	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224170604	495032	0	0
T5	265	122	0	0
T6	0	157	0	0
T8	1957	1120	0	0
T9	0	204	0	0
T13	0	970	0	0
T14	138	0	0	0
T20	0	622	0	0
T23	0	785	0	0
T26	848	0	0	0
T27	3218	0	0	0
T31	0	473	0	0
T32	0	348	0	0
T40	593300	0	0	0
T43	3631	0	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T47	1939	0	0	0
T95	0	305	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	224364090	544359	0	0
T5	805	400	0	0
T8	1957	1120	0	0
T9	0	204	0	0
T13	0	970	0	0
T14	685	109	0	0
T15	0	111	0	0
T20	0	622	0	0
T26	848	0	0	0
T27	3218	0	0	0
T31	0	473	0	0
T32	0	348	0	0
T40	593300	0	0	0
T43	3631	0	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T47	1939	0	0	0
T64	0	119	0	0