Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.25 98.24 93.82 97.01 81.50 96.76 99.77 92.64


Total test records in report: 974
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T785 /workspace/coverage/default/49.edn_disable_auto_req_mode.3409331364 May 02 02:53:26 PM PDT 24 May 02 02:53:29 PM PDT 24 60342210 ps
T786 /workspace/coverage/default/219.edn_genbits.81315076 May 02 02:54:14 PM PDT 24 May 02 02:54:17 PM PDT 24 49951563 ps
T787 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2283965167 May 02 02:52:58 PM PDT 24 May 02 03:28:33 PM PDT 24 372147845495 ps
T788 /workspace/coverage/default/268.edn_genbits.165263954 May 02 02:54:25 PM PDT 24 May 02 02:54:28 PM PDT 24 33250031 ps
T789 /workspace/coverage/default/11.edn_disable.1422212548 May 02 02:51:56 PM PDT 24 May 02 02:51:59 PM PDT 24 21121341 ps
T790 /workspace/coverage/default/2.edn_smoke.338347499 May 02 02:51:24 PM PDT 24 May 02 02:51:26 PM PDT 24 133778334 ps
T791 /workspace/coverage/default/0.edn_alert_test.387328300 May 02 02:51:25 PM PDT 24 May 02 02:51:28 PM PDT 24 17637444 ps
T792 /workspace/coverage/default/5.edn_smoke.3054821419 May 02 02:51:41 PM PDT 24 May 02 02:51:43 PM PDT 24 21082486 ps
T793 /workspace/coverage/default/29.edn_err.3246663072 May 02 02:52:32 PM PDT 24 May 02 02:52:34 PM PDT 24 31256590 ps
T794 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2907600866 May 02 02:52:19 PM PDT 24 May 02 02:57:34 PM PDT 24 52210974955 ps
T181 /workspace/coverage/default/42.edn_err.1177560370 May 02 02:53:11 PM PDT 24 May 02 02:53:14 PM PDT 24 96515204 ps
T795 /workspace/coverage/default/20.edn_alert.4262058558 May 02 02:52:16 PM PDT 24 May 02 02:52:18 PM PDT 24 47602485 ps
T796 /workspace/coverage/default/48.edn_alert_test.2107121865 May 02 02:53:24 PM PDT 24 May 02 02:53:26 PM PDT 24 38477962 ps
T797 /workspace/coverage/default/37.edn_smoke.3908851504 May 02 02:52:58 PM PDT 24 May 02 02:53:01 PM PDT 24 18787418 ps
T798 /workspace/coverage/default/3.edn_alert.3093976573 May 02 02:51:33 PM PDT 24 May 02 02:51:36 PM PDT 24 202406650 ps
T799 /workspace/coverage/default/9.edn_alert.3210308171 May 02 02:51:49 PM PDT 24 May 02 02:51:52 PM PDT 24 195317970 ps
T800 /workspace/coverage/default/12.edn_disable_auto_req_mode.4002607729 May 02 02:51:55 PM PDT 24 May 02 02:51:58 PM PDT 24 78906905 ps
T801 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.851343566 May 02 02:51:46 PM PDT 24 May 02 03:22:08 PM PDT 24 70993036812 ps
T802 /workspace/coverage/default/76.edn_genbits.1440663636 May 02 02:53:38 PM PDT 24 May 02 02:53:41 PM PDT 24 38266396 ps
T803 /workspace/coverage/default/29.edn_disable_auto_req_mode.192843704 May 02 02:52:35 PM PDT 24 May 02 02:52:38 PM PDT 24 96247681 ps
T804 /workspace/coverage/default/92.edn_genbits.3458980873 May 02 02:53:44 PM PDT 24 May 02 02:53:47 PM PDT 24 101160107 ps
T99 /workspace/coverage/default/46.edn_intr.1356753678 May 02 02:53:21 PM PDT 24 May 02 02:53:22 PM PDT 24 24229722 ps
T805 /workspace/coverage/default/265.edn_genbits.1149691270 May 02 02:54:25 PM PDT 24 May 02 02:54:28 PM PDT 24 54739941 ps
T806 /workspace/coverage/default/10.edn_alert.327517206 May 02 02:51:56 PM PDT 24 May 02 02:51:59 PM PDT 24 76864185 ps
T807 /workspace/coverage/default/37.edn_alert_test.1763154720 May 02 02:52:56 PM PDT 24 May 02 02:52:59 PM PDT 24 16182603 ps
T808 /workspace/coverage/default/78.edn_genbits.2670579858 May 02 02:53:38 PM PDT 24 May 02 02:53:41 PM PDT 24 80671332 ps
T809 /workspace/coverage/default/291.edn_genbits.200581478 May 02 02:54:28 PM PDT 24 May 02 02:54:31 PM PDT 24 72260680 ps
T810 /workspace/coverage/default/47.edn_intr.2433238240 May 02 02:53:25 PM PDT 24 May 02 02:53:28 PM PDT 24 21194688 ps
T811 /workspace/coverage/default/80.edn_err.205124475 May 02 02:53:36 PM PDT 24 May 02 02:53:38 PM PDT 24 39506928 ps
T812 /workspace/coverage/default/36.edn_err.1326965111 May 02 02:52:56 PM PDT 24 May 02 02:52:59 PM PDT 24 72725848 ps
T813 /workspace/coverage/default/182.edn_genbits.4176903883 May 02 02:54:13 PM PDT 24 May 02 02:54:23 PM PDT 24 1040646591 ps
T814 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2419303471 May 02 02:52:15 PM PDT 24 May 02 03:26:58 PM PDT 24 314732688883 ps
T815 /workspace/coverage/default/256.edn_genbits.1055731867 May 02 02:54:18 PM PDT 24 May 02 02:54:21 PM PDT 24 102669010 ps
T816 /workspace/coverage/default/297.edn_genbits.600349770 May 02 02:54:32 PM PDT 24 May 02 02:54:34 PM PDT 24 41274495 ps
T817 /workspace/coverage/default/277.edn_genbits.2158831640 May 02 02:54:24 PM PDT 24 May 02 02:54:27 PM PDT 24 63256861 ps
T818 /workspace/coverage/default/281.edn_genbits.3064581055 May 02 02:54:35 PM PDT 24 May 02 02:54:37 PM PDT 24 228712972 ps
T819 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1828016073 May 02 02:52:03 PM PDT 24 May 02 03:28:38 PM PDT 24 399446320899 ps
T820 /workspace/coverage/default/24.edn_smoke.2429361012 May 02 02:52:24 PM PDT 24 May 02 02:52:26 PM PDT 24 45717446 ps
T821 /workspace/coverage/default/37.edn_intr.3547859971 May 02 02:52:57 PM PDT 24 May 02 02:53:00 PM PDT 24 27096401 ps
T822 /workspace/coverage/default/25.edn_alert.2185889951 May 02 02:52:28 PM PDT 24 May 02 02:52:31 PM PDT 24 90873960 ps
T141 /workspace/coverage/default/91.edn_err.747395793 May 02 02:53:42 PM PDT 24 May 02 02:53:44 PM PDT 24 29722402 ps
T823 /workspace/coverage/default/17.edn_alert.2531323274 May 02 02:52:07 PM PDT 24 May 02 02:52:10 PM PDT 24 54590953 ps
T824 /workspace/coverage/default/87.edn_genbits.1814210185 May 02 02:53:38 PM PDT 24 May 02 02:53:41 PM PDT 24 60648988 ps
T825 /workspace/coverage/default/42.edn_alert_test.1187439917 May 02 02:53:09 PM PDT 24 May 02 02:53:11 PM PDT 24 23873224 ps
T826 /workspace/coverage/default/39.edn_stress_all.2715581503 May 02 02:53:03 PM PDT 24 May 02 02:53:10 PM PDT 24 300308713 ps
T827 /workspace/coverage/default/34.edn_stress_all.2214485264 May 02 02:52:48 PM PDT 24 May 02 02:52:50 PM PDT 24 90533276 ps
T828 /workspace/coverage/default/183.edn_genbits.522909369 May 02 02:54:02 PM PDT 24 May 02 02:54:05 PM PDT 24 36889880 ps
T829 /workspace/coverage/default/223.edn_genbits.554562651 May 02 02:54:14 PM PDT 24 May 02 02:54:17 PM PDT 24 85346374 ps
T830 /workspace/coverage/default/21.edn_alert_test.1391956458 May 02 02:52:18 PM PDT 24 May 02 02:52:20 PM PDT 24 63523500 ps
T831 /workspace/coverage/default/41.edn_intr.1626248395 May 02 02:53:07 PM PDT 24 May 02 02:53:09 PM PDT 24 40473627 ps
T832 /workspace/coverage/default/23.edn_genbits.3564611698 May 02 02:52:24 PM PDT 24 May 02 02:52:27 PM PDT 24 29304552 ps
T833 /workspace/coverage/default/193.edn_genbits.559251832 May 02 02:54:12 PM PDT 24 May 02 02:54:16 PM PDT 24 131796042 ps
T834 /workspace/coverage/default/35.edn_smoke.3874862012 May 02 02:52:50 PM PDT 24 May 02 02:52:53 PM PDT 24 46986417 ps
T835 /workspace/coverage/default/30.edn_stress_all.2570753287 May 02 02:52:40 PM PDT 24 May 02 02:52:47 PM PDT 24 755061757 ps
T836 /workspace/coverage/default/42.edn_smoke.2236334978 May 02 02:53:04 PM PDT 24 May 02 02:53:06 PM PDT 24 43555009 ps
T837 /workspace/coverage/default/28.edn_genbits.3159322847 May 02 02:52:32 PM PDT 24 May 02 02:52:35 PM PDT 24 106788250 ps
T838 /workspace/coverage/default/292.edn_genbits.768532459 May 02 02:54:31 PM PDT 24 May 02 02:54:34 PM PDT 24 57990166 ps
T839 /workspace/coverage/default/44.edn_disable_auto_req_mode.4110029660 May 02 02:53:11 PM PDT 24 May 02 02:53:14 PM PDT 24 38931439 ps
T840 /workspace/coverage/default/33.edn_alert_test.4129526793 May 02 02:52:55 PM PDT 24 May 02 02:52:58 PM PDT 24 39286926 ps
T243 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.621556151 May 02 02:49:51 PM PDT 24 May 02 02:49:54 PM PDT 24 143964978 ps
T219 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4092053677 May 02 02:49:04 PM PDT 24 May 02 02:49:07 PM PDT 24 41745348 ps
T841 /workspace/coverage/cover_reg_top/44.edn_intr_test.2767455222 May 02 02:50:18 PM PDT 24 May 02 02:50:20 PM PDT 24 78336584 ps
T244 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2304377094 May 02 02:49:56 PM PDT 24 May 02 02:50:00 PM PDT 24 102212956 ps
T842 /workspace/coverage/cover_reg_top/30.edn_intr_test.243909906 May 02 02:50:10 PM PDT 24 May 02 02:50:13 PM PDT 24 52879082 ps
T843 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2788186906 May 02 02:49:30 PM PDT 24 May 02 02:49:33 PM PDT 24 40300327 ps
T844 /workspace/coverage/cover_reg_top/38.edn_intr_test.3307410517 May 02 02:50:08 PM PDT 24 May 02 02:50:11 PM PDT 24 30219363 ps
T220 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1235746050 May 02 02:49:04 PM PDT 24 May 02 02:49:07 PM PDT 24 49250306 ps
T221 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4230415908 May 02 02:49:58 PM PDT 24 May 02 02:50:01 PM PDT 24 43838058 ps
T245 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.202075211 May 02 02:49:38 PM PDT 24 May 02 02:49:42 PM PDT 24 554542044 ps
T238 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4145369486 May 02 02:49:53 PM PDT 24 May 02 02:49:55 PM PDT 24 64195147 ps
T222 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1110295391 May 02 02:48:43 PM PDT 24 May 02 02:48:45 PM PDT 24 21392018 ps
T242 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2056593572 May 02 02:49:55 PM PDT 24 May 02 02:49:57 PM PDT 24 48952973 ps
T249 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.574851282 May 02 02:49:38 PM PDT 24 May 02 02:49:42 PM PDT 24 97009577 ps
T845 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2490658857 May 02 02:49:04 PM PDT 24 May 02 02:49:07 PM PDT 24 40188132 ps
T846 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2733093546 May 02 02:49:19 PM PDT 24 May 02 02:49:22 PM PDT 24 264916962 ps
T847 /workspace/coverage/cover_reg_top/36.edn_intr_test.3217839713 May 02 02:50:08 PM PDT 24 May 02 02:50:11 PM PDT 24 101390267 ps
T848 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.410941497 May 02 02:49:48 PM PDT 24 May 02 02:49:51 PM PDT 24 41015464 ps
T223 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2046737719 May 02 02:49:42 PM PDT 24 May 02 02:49:44 PM PDT 24 58251232 ps
T849 /workspace/coverage/cover_reg_top/25.edn_intr_test.2418483358 May 02 02:50:11 PM PDT 24 May 02 02:50:14 PM PDT 24 11142787 ps
T251 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1641162019 May 02 02:50:01 PM PDT 24 May 02 02:50:05 PM PDT 24 102195363 ps
T850 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.297194979 May 02 02:50:05 PM PDT 24 May 02 02:50:08 PM PDT 24 16719397 ps
T851 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.630297562 May 02 02:49:29 PM PDT 24 May 02 02:49:32 PM PDT 24 56300936 ps
T852 /workspace/coverage/cover_reg_top/18.edn_intr_test.3994327052 May 02 02:49:54 PM PDT 24 May 02 02:49:56 PM PDT 24 28570346 ps
T853 /workspace/coverage/cover_reg_top/35.edn_intr_test.1087489186 May 02 02:50:09 PM PDT 24 May 02 02:50:13 PM PDT 24 15146902 ps
T854 /workspace/coverage/cover_reg_top/7.edn_tl_errors.4181931315 May 02 02:49:30 PM PDT 24 May 02 02:49:35 PM PDT 24 321215007 ps
T855 /workspace/coverage/cover_reg_top/9.edn_intr_test.4007963274 May 02 02:49:36 PM PDT 24 May 02 02:49:38 PM PDT 24 23785481 ps
T856 /workspace/coverage/cover_reg_top/41.edn_intr_test.3186443344 May 02 02:50:20 PM PDT 24 May 02 02:50:22 PM PDT 24 15860594 ps
T224 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.864943458 May 02 02:49:17 PM PDT 24 May 02 02:49:21 PM PDT 24 41029259 ps
T225 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2481862817 May 02 02:49:51 PM PDT 24 May 02 02:49:53 PM PDT 24 49214340 ps
T857 /workspace/coverage/cover_reg_top/27.edn_intr_test.353770292 May 02 02:50:07 PM PDT 24 May 02 02:50:09 PM PDT 24 11881848 ps
T858 /workspace/coverage/cover_reg_top/1.edn_intr_test.1684826991 May 02 02:48:50 PM PDT 24 May 02 02:48:52 PM PDT 24 44544851 ps
T859 /workspace/coverage/cover_reg_top/17.edn_tl_errors.679393818 May 02 02:49:55 PM PDT 24 May 02 02:49:59 PM PDT 24 42397131 ps
T239 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3480403464 May 02 02:49:35 PM PDT 24 May 02 02:49:38 PM PDT 24 19696534 ps
T226 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2548977398 May 02 02:48:50 PM PDT 24 May 02 02:48:53 PM PDT 24 56151944 ps
T860 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3606781664 May 02 02:49:42 PM PDT 24 May 02 02:49:44 PM PDT 24 27646044 ps
T227 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.812066719 May 02 02:48:48 PM PDT 24 May 02 02:48:50 PM PDT 24 112231172 ps
T861 /workspace/coverage/cover_reg_top/2.edn_intr_test.927067428 May 02 02:48:58 PM PDT 24 May 02 02:49:00 PM PDT 24 21108565 ps
T862 /workspace/coverage/cover_reg_top/33.edn_intr_test.1948100984 May 02 02:50:12 PM PDT 24 May 02 02:50:15 PM PDT 24 16609787 ps
T863 /workspace/coverage/cover_reg_top/16.edn_intr_test.2149608807 May 02 02:49:50 PM PDT 24 May 02 02:49:52 PM PDT 24 11020589 ps
T240 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2237982185 May 02 02:49:28 PM PDT 24 May 02 02:49:30 PM PDT 24 72419789 ps
T864 /workspace/coverage/cover_reg_top/32.edn_intr_test.3352214046 May 02 02:50:08 PM PDT 24 May 02 02:50:10 PM PDT 24 21479630 ps
T865 /workspace/coverage/cover_reg_top/34.edn_intr_test.597349457 May 02 02:50:10 PM PDT 24 May 02 02:50:14 PM PDT 24 12704948 ps
T228 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1336816033 May 02 02:49:05 PM PDT 24 May 02 02:49:07 PM PDT 24 54595018 ps
T866 /workspace/coverage/cover_reg_top/15.edn_intr_test.3546471679 May 02 02:49:53 PM PDT 24 May 02 02:49:55 PM PDT 24 14142529 ps
T241 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4106974775 May 02 02:49:30 PM PDT 24 May 02 02:49:33 PM PDT 24 78295419 ps
T867 /workspace/coverage/cover_reg_top/20.edn_intr_test.3083527658 May 02 02:50:03 PM PDT 24 May 02 02:50:04 PM PDT 24 17484487 ps
T868 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2739376803 May 02 02:49:11 PM PDT 24 May 02 02:49:13 PM PDT 24 44237446 ps
T869 /workspace/coverage/cover_reg_top/45.edn_intr_test.3662396899 May 02 02:50:17 PM PDT 24 May 02 02:50:19 PM PDT 24 18954316 ps
T250 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1713573601 May 02 02:49:11 PM PDT 24 May 02 02:49:15 PM PDT 24 93730623 ps
T870 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4008655370 May 02 02:49:30 PM PDT 24 May 02 02:49:33 PM PDT 24 19214727 ps
T871 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1048840301 May 02 02:49:46 PM PDT 24 May 02 02:49:51 PM PDT 24 223350184 ps
T872 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1687627030 May 02 02:49:31 PM PDT 24 May 02 02:49:34 PM PDT 24 25055936 ps
T873 /workspace/coverage/cover_reg_top/21.edn_intr_test.1932249269 May 02 02:50:01 PM PDT 24 May 02 02:50:03 PM PDT 24 42209861 ps
T874 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1590856550 May 02 02:49:41 PM PDT 24 May 02 02:49:43 PM PDT 24 57541147 ps
T875 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3749793231 May 02 02:49:32 PM PDT 24 May 02 02:49:36 PM PDT 24 96915649 ps
T876 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4156623086 May 02 02:49:36 PM PDT 24 May 02 02:49:38 PM PDT 24 15521510 ps
T877 /workspace/coverage/cover_reg_top/28.edn_intr_test.2847982535 May 02 02:50:13 PM PDT 24 May 02 02:50:16 PM PDT 24 36745804 ps
T878 /workspace/coverage/cover_reg_top/29.edn_intr_test.2488014862 May 02 02:50:12 PM PDT 24 May 02 02:50:15 PM PDT 24 24337317 ps
T252 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3628047505 May 02 02:49:42 PM PDT 24 May 02 02:49:46 PM PDT 24 101395442 ps
T879 /workspace/coverage/cover_reg_top/5.edn_intr_test.2855897118 May 02 02:49:19 PM PDT 24 May 02 02:49:21 PM PDT 24 20306831 ps
T229 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2413358237 May 02 02:49:31 PM PDT 24 May 02 02:49:33 PM PDT 24 40206525 ps
T880 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1209379788 May 02 02:49:17 PM PDT 24 May 02 02:49:20 PM PDT 24 351502830 ps
T881 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1185685219 May 02 02:49:30 PM PDT 24 May 02 02:49:33 PM PDT 24 53024200 ps
T882 /workspace/coverage/cover_reg_top/47.edn_intr_test.3867303396 May 02 02:50:20 PM PDT 24 May 02 02:50:22 PM PDT 24 50804651 ps
T883 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2581563398 May 02 02:49:24 PM PDT 24 May 02 02:49:28 PM PDT 24 418012581 ps
T884 /workspace/coverage/cover_reg_top/4.edn_intr_test.1714052354 May 02 02:49:12 PM PDT 24 May 02 02:49:15 PM PDT 24 45076028 ps
T885 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1612396944 May 02 02:48:56 PM PDT 24 May 02 02:49:00 PM PDT 24 158121872 ps
T886 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3719039703 May 02 02:50:05 PM PDT 24 May 02 02:50:07 PM PDT 24 22085824 ps
T887 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3148572180 May 02 02:49:38 PM PDT 24 May 02 02:49:40 PM PDT 24 97073801 ps
T888 /workspace/coverage/cover_reg_top/8.edn_intr_test.4115041487 May 02 02:49:31 PM PDT 24 May 02 02:49:34 PM PDT 24 21310914 ps
T889 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3317624112 May 02 02:49:32 PM PDT 24 May 02 02:49:35 PM PDT 24 33670601 ps
T890 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1167076897 May 02 02:48:46 PM PDT 24 May 02 02:48:50 PM PDT 24 81409000 ps
T891 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3180585950 May 02 02:49:25 PM PDT 24 May 02 02:49:27 PM PDT 24 75411682 ps
T892 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2775975752 May 02 02:49:54 PM PDT 24 May 02 02:49:56 PM PDT 24 85680510 ps
T230 /workspace/coverage/cover_reg_top/13.edn_csr_rw.139090203 May 02 02:49:43 PM PDT 24 May 02 02:49:44 PM PDT 24 10823943 ps
T893 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1099459998 May 02 02:49:56 PM PDT 24 May 02 02:49:59 PM PDT 24 74550856 ps
T894 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1720229168 May 02 02:49:12 PM PDT 24 May 02 02:49:16 PM PDT 24 55435236 ps
T895 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3190124855 May 02 02:49:48 PM PDT 24 May 02 02:49:50 PM PDT 24 63501733 ps
T896 /workspace/coverage/cover_reg_top/43.edn_intr_test.384464309 May 02 02:50:18 PM PDT 24 May 02 02:50:21 PM PDT 24 18913284 ps
T235 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4294354176 May 02 02:49:03 PM PDT 24 May 02 02:49:08 PM PDT 24 268019624 ps
T231 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.191410045 May 02 02:49:04 PM PDT 24 May 02 02:49:06 PM PDT 24 31167576 ps
T897 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1548664391 May 02 02:49:42 PM PDT 24 May 02 02:49:44 PM PDT 24 21921734 ps
T898 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1081484786 May 02 02:49:25 PM PDT 24 May 02 02:49:27 PM PDT 24 52792712 ps
T899 /workspace/coverage/cover_reg_top/42.edn_intr_test.3715253560 May 02 02:50:17 PM PDT 24 May 02 02:50:19 PM PDT 24 13350564 ps
T232 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4229873756 May 02 02:48:51 PM PDT 24 May 02 02:48:54 PM PDT 24 78560540 ps
T900 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1524393028 May 02 02:49:51 PM PDT 24 May 02 02:49:53 PM PDT 24 23197228 ps
T901 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.16591908 May 02 02:49:58 PM PDT 24 May 02 02:50:01 PM PDT 24 39719804 ps
T902 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3988838795 May 02 02:49:50 PM PDT 24 May 02 02:49:52 PM PDT 24 373297099 ps
T903 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1459649239 May 02 02:48:47 PM PDT 24 May 02 02:48:53 PM PDT 24 229051941 ps
T904 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2627345427 May 02 02:49:27 PM PDT 24 May 02 02:49:30 PM PDT 24 26676628 ps
T905 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3867334557 May 02 02:49:54 PM PDT 24 May 02 02:49:57 PM PDT 24 88599579 ps
T906 /workspace/coverage/cover_reg_top/19.edn_intr_test.2250281598 May 02 02:50:01 PM PDT 24 May 02 02:50:03 PM PDT 24 15612713 ps
T907 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1174440666 May 02 02:49:31 PM PDT 24 May 02 02:49:35 PM PDT 24 112452788 ps
T908 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2869658724 May 02 02:48:57 PM PDT 24 May 02 02:49:04 PM PDT 24 358125329 ps
T909 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.355832076 May 02 02:48:44 PM PDT 24 May 02 02:48:49 PM PDT 24 60407137 ps
T910 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1273588486 May 02 02:48:57 PM PDT 24 May 02 02:49:00 PM PDT 24 32456334 ps
T911 /workspace/coverage/cover_reg_top/1.edn_csr_rw.83651958 May 02 02:48:58 PM PDT 24 May 02 02:49:00 PM PDT 24 17637876 ps
T912 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3950574423 May 02 02:48:51 PM PDT 24 May 02 02:48:55 PM PDT 24 75311549 ps
T913 /workspace/coverage/cover_reg_top/48.edn_intr_test.1365023204 May 02 02:50:21 PM PDT 24 May 02 02:50:22 PM PDT 24 25651182 ps
T914 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3705293445 May 02 02:49:49 PM PDT 24 May 02 02:49:52 PM PDT 24 132942899 ps
T915 /workspace/coverage/cover_reg_top/13.edn_intr_test.2874472677 May 02 02:49:43 PM PDT 24 May 02 02:49:45 PM PDT 24 60409386 ps
T916 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.334032954 May 02 02:49:37 PM PDT 24 May 02 02:49:40 PM PDT 24 105925225 ps
T917 /workspace/coverage/cover_reg_top/5.edn_tl_errors.740592762 May 02 02:49:17 PM PDT 24 May 02 02:49:22 PM PDT 24 141173833 ps
T918 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1145861024 May 02 02:49:31 PM PDT 24 May 02 02:49:33 PM PDT 24 24652851 ps
T919 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2510159013 May 02 02:49:11 PM PDT 24 May 02 02:49:14 PM PDT 24 12157573 ps
T920 /workspace/coverage/cover_reg_top/49.edn_intr_test.3727959307 May 02 02:50:16 PM PDT 24 May 02 02:50:18 PM PDT 24 17512872 ps
T921 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.716415045 May 02 02:48:57 PM PDT 24 May 02 02:49:00 PM PDT 24 41867883 ps
T233 /workspace/coverage/cover_reg_top/5.edn_csr_rw.816257198 May 02 02:49:18 PM PDT 24 May 02 02:49:21 PM PDT 24 14596330 ps
T922 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2608923062 May 02 02:49:38 PM PDT 24 May 02 02:49:41 PM PDT 24 843328634 ps
T923 /workspace/coverage/cover_reg_top/6.edn_intr_test.3784650880 May 02 02:49:25 PM PDT 24 May 02 02:49:27 PM PDT 24 40584810 ps
T924 /workspace/coverage/cover_reg_top/14.edn_intr_test.69117898 May 02 02:49:43 PM PDT 24 May 02 02:49:45 PM PDT 24 37916610 ps
T925 /workspace/coverage/cover_reg_top/10.edn_intr_test.2884323070 May 02 02:49:37 PM PDT 24 May 02 02:49:39 PM PDT 24 13758565 ps
T926 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3172994937 May 02 02:49:30 PM PDT 24 May 02 02:49:33 PM PDT 24 81701018 ps
T927 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3226083287 May 02 02:48:50 PM PDT 24 May 02 02:48:53 PM PDT 24 51604327 ps
T928 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2115390489 May 02 02:49:49 PM PDT 24 May 02 02:49:52 PM PDT 24 85393354 ps
T929 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3548902179 May 02 02:49:56 PM PDT 24 May 02 02:49:58 PM PDT 24 45411521 ps
T930 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4013505398 May 02 02:49:37 PM PDT 24 May 02 02:49:39 PM PDT 24 22159757 ps
T931 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2870225822 May 02 02:49:11 PM PDT 24 May 02 02:49:14 PM PDT 24 24478406 ps
T234 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3275586740 May 02 02:50:01 PM PDT 24 May 02 02:50:03 PM PDT 24 45193203 ps
T932 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3197790237 May 02 02:49:44 PM PDT 24 May 02 02:49:46 PM PDT 24 68844185 ps
T933 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3616279965 May 02 02:50:02 PM PDT 24 May 02 02:50:06 PM PDT 24 127745576 ps
T934 /workspace/coverage/cover_reg_top/11.edn_tl_errors.858737146 May 02 02:49:37 PM PDT 24 May 02 02:49:42 PM PDT 24 194432755 ps
T935 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2618027026 May 02 02:49:30 PM PDT 24 May 02 02:49:34 PM PDT 24 622221025 ps
T936 /workspace/coverage/cover_reg_top/3.edn_tl_errors.549246348 May 02 02:49:04 PM PDT 24 May 02 02:49:07 PM PDT 24 46090668 ps
T937 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2497753658 May 02 02:49:41 PM PDT 24 May 02 02:49:43 PM PDT 24 16320105 ps
T938 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.447340046 May 02 02:50:01 PM PDT 24 May 02 02:50:03 PM PDT 24 55660097 ps
T939 /workspace/coverage/cover_reg_top/46.edn_intr_test.2776043290 May 02 02:50:17 PM PDT 24 May 02 02:50:19 PM PDT 24 44931430 ps
T940 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3879411292 May 02 02:49:39 PM PDT 24 May 02 02:49:41 PM PDT 24 25610388 ps
T941 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.505153759 May 02 02:49:18 PM PDT 24 May 02 02:49:23 PM PDT 24 131344045 ps
T942 /workspace/coverage/cover_reg_top/0.edn_intr_test.4265906900 May 02 02:48:46 PM PDT 24 May 02 02:48:48 PM PDT 24 15685130 ps
T236 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2764195635 May 02 02:49:10 PM PDT 24 May 02 02:49:12 PM PDT 24 19135966 ps
T943 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2926890411 May 02 02:49:54 PM PDT 24 May 02 02:49:56 PM PDT 24 22338695 ps
T944 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3931154098 May 02 02:49:18 PM PDT 24 May 02 02:49:22 PM PDT 24 333904334 ps
T945 /workspace/coverage/cover_reg_top/23.edn_intr_test.3036310994 May 02 02:50:13 PM PDT 24 May 02 02:50:16 PM PDT 24 41871403 ps
T946 /workspace/coverage/cover_reg_top/31.edn_intr_test.1929669323 May 02 02:50:10 PM PDT 24 May 02 02:50:13 PM PDT 24 18760079 ps
T947 /workspace/coverage/cover_reg_top/2.edn_tl_errors.613821254 May 02 02:48:58 PM PDT 24 May 02 02:49:03 PM PDT 24 112973690 ps
T948 /workspace/coverage/cover_reg_top/14.edn_csr_rw.4193584606 May 02 02:49:50 PM PDT 24 May 02 02:49:52 PM PDT 24 11385559 ps
T949 /workspace/coverage/cover_reg_top/40.edn_intr_test.2123375834 May 02 02:50:18 PM PDT 24 May 02 02:50:20 PM PDT 24 52163729 ps
T950 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2792693300 May 02 02:49:25 PM PDT 24 May 02 02:49:27 PM PDT 24 74064010 ps
T951 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1668134955 May 02 02:49:36 PM PDT 24 May 02 02:49:38 PM PDT 24 179195870 ps
T952 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3584048729 May 02 02:49:03 PM PDT 24 May 02 02:49:06 PM PDT 24 34887043 ps
T953 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1776791265 May 02 02:48:50 PM PDT 24 May 02 02:48:53 PM PDT 24 50582302 ps
T954 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1694638809 May 02 02:49:31 PM PDT 24 May 02 02:49:34 PM PDT 24 42393637 ps
T955 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3252643400 May 02 02:50:00 PM PDT 24 May 02 02:50:03 PM PDT 24 22569735 ps
T956 /workspace/coverage/cover_reg_top/26.edn_intr_test.2671054802 May 02 02:50:09 PM PDT 24 May 02 02:50:12 PM PDT 24 71756679 ps
T957 /workspace/coverage/cover_reg_top/39.edn_intr_test.2252488283 May 02 02:50:08 PM PDT 24 May 02 02:50:11 PM PDT 24 14914315 ps
T958 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.406734674 May 02 02:49:36 PM PDT 24 May 02 02:49:39 PM PDT 24 21306129 ps
T959 /workspace/coverage/cover_reg_top/7.edn_intr_test.1681096099 May 02 02:49:36 PM PDT 24 May 02 02:49:38 PM PDT 24 59033254 ps
T960 /workspace/coverage/cover_reg_top/17.edn_intr_test.1283109228 May 02 02:49:54 PM PDT 24 May 02 02:49:56 PM PDT 24 34220467 ps
T237 /workspace/coverage/cover_reg_top/2.edn_csr_rw.192967587 May 02 02:48:57 PM PDT 24 May 02 02:48:59 PM PDT 24 31189092 ps
T961 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3846952846 May 02 02:48:50 PM PDT 24 May 02 02:48:54 PM PDT 24 519523033 ps
T962 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1084537817 May 02 02:49:11 PM PDT 24 May 02 02:49:15 PM PDT 24 81049763 ps
T963 /workspace/coverage/cover_reg_top/11.edn_intr_test.2818314794 May 02 02:49:37 PM PDT 24 May 02 02:49:39 PM PDT 24 124909571 ps
T964 /workspace/coverage/cover_reg_top/12.edn_intr_test.2158890562 May 02 02:49:38 PM PDT 24 May 02 02:49:40 PM PDT 24 15110925 ps
T965 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1484507765 May 02 02:49:55 PM PDT 24 May 02 02:50:01 PM PDT 24 287195417 ps
T966 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2647751771 May 02 02:49:43 PM PDT 24 May 02 02:49:46 PM PDT 24 85648162 ps
T967 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2499887179 May 02 02:48:58 PM PDT 24 May 02 02:49:01 PM PDT 24 76486909 ps
T968 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4094986518 May 02 02:49:04 PM PDT 24 May 02 02:49:07 PM PDT 24 155214540 ps
T969 /workspace/coverage/cover_reg_top/13.edn_tl_errors.896059235 May 02 02:49:43 PM PDT 24 May 02 02:49:46 PM PDT 24 110211121 ps
T970 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3494392254 May 02 02:48:57 PM PDT 24 May 02 02:49:00 PM PDT 24 104138437 ps
T971 /workspace/coverage/cover_reg_top/24.edn_intr_test.1805131668 May 02 02:50:09 PM PDT 24 May 02 02:50:12 PM PDT 24 27997607 ps
T972 /workspace/coverage/cover_reg_top/37.edn_intr_test.4179498333 May 02 02:50:09 PM PDT 24 May 02 02:50:13 PM PDT 24 57474709 ps
T973 /workspace/coverage/cover_reg_top/22.edn_intr_test.2028605176 May 02 02:50:10 PM PDT 24 May 02 02:50:13 PM PDT 24 13038609 ps
T974 /workspace/coverage/cover_reg_top/3.edn_intr_test.3917756854 May 02 02:49:05 PM PDT 24 May 02 02:49:08 PM PDT 24 14788681 ps

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4130780029
Short name T8
Test name
Test status
Simulation time 36134325 ps
CPU time 1.36 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 216960 kb
Host smart-b4d5325f-dd17-4d58-b593-de6968917358
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130780029 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4130780029
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/240.edn_genbits.2939666936
Short name T39
Test name
Test status
Simulation time 107439218 ps
CPU time 1.55 seconds
Started May 02 02:54:16 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 218112 kb
Host smart-fbf4eaa1-6945-41bd-9a0e-5394ac935d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939666936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2939666936
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.90998731
Short name T34
Test name
Test status
Simulation time 53910757526 ps
CPU time 1388.75 seconds
Started May 02 02:52:07 PM PDT 24
Finished May 02 03:15:17 PM PDT 24
Peak memory 223272 kb
Host smart-c00744ec-537a-4f04-ad91-41dfcb89473d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90998731 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.90998731
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_err.3203456624
Short name T13
Test name
Test status
Simulation time 28946125 ps
CPU time 1.28 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 225560 kb
Host smart-08036248-47f8-4000-bbc9-8fa840a93914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203456624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3203456624
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4230961260
Short name T17
Test name
Test status
Simulation time 243380294 ps
CPU time 3.97 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:31 PM PDT 24
Peak memory 236476 kb
Host smart-1e001ef1-45a5-455f-80fb-2140261493e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230961260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4230961260
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/21.edn_alert.106238099
Short name T24
Test name
Test status
Simulation time 49762472 ps
CPU time 1.26 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 215584 kb
Host smart-64ce0cd8-198e-4252-8698-171c2dcd8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106238099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.106238099
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/73.edn_genbits.4070476909
Short name T18
Test name
Test status
Simulation time 73391147 ps
CPU time 1.4 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 218232 kb
Host smart-a92f5ac1-248b-4432-8176-8b2e2834ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070476909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4070476909
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all.1284444095
Short name T156
Test name
Test status
Simulation time 132618755 ps
CPU time 1.89 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:52:00 PM PDT 24
Peak memory 216712 kb
Host smart-a2765ba8-538a-4a0c-9164-01be746ace9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284444095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1284444095
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.2877306935
Short name T114
Test name
Test status
Simulation time 31453449 ps
CPU time 0.92 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 218564 kb
Host smart-941ef993-1d5b-4a52-8d94-aa1e69eb8783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877306935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2877306935
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/7.edn_regwen.2871517535
Short name T21
Test name
Test status
Simulation time 28385148 ps
CPU time 0.98 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 206984 kb
Host smart-8078bf01-4ed7-4b3f-8171-6c9451dbfa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871517535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2871517535
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/34.edn_genbits.197748432
Short name T10
Test name
Test status
Simulation time 39006429 ps
CPU time 1.5 seconds
Started May 02 02:52:49 PM PDT 24
Finished May 02 02:52:51 PM PDT 24
Peak memory 218092 kb
Host smart-c0c813f3-f93b-46e2-8a7f-0f5d11cb7077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197748432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.197748432
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_alert.1447510888
Short name T26
Test name
Test status
Simulation time 24465621 ps
CPU time 1.14 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215592 kb
Host smart-769a1904-5444-496a-acad-688eae784c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447510888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1447510888
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert.2756950984
Short name T261
Test name
Test status
Simulation time 26901509 ps
CPU time 1.19 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:11 PM PDT 24
Peak memory 215548 kb
Host smart-33c03956-a383-450f-a7c5-e08c6185619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756950984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2756950984
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/30.edn_intr.1496327327
Short name T52
Test name
Test status
Simulation time 21773108 ps
CPU time 1.13 seconds
Started May 02 02:52:42 PM PDT 24
Finished May 02 02:52:45 PM PDT 24
Peak memory 223824 kb
Host smart-471111f3-fddb-4b50-a657-a83d72e749c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496327327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1496327327
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/35.edn_alert.2000258670
Short name T93
Test name
Test status
Simulation time 159608723 ps
CPU time 1.26 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:58 PM PDT 24
Peak memory 215512 kb
Host smart-96b91575-56d6-4648-8607-c320b1aead07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000258670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2000258670
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.716343296
Short name T35
Test name
Test status
Simulation time 30307577062 ps
CPU time 341.38 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:57:21 PM PDT 24
Peak memory 220168 kb
Host smart-e70fc038-bcf7-460c-a0a0-98ff40ba29dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716343296 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.716343296
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.574851282
Short name T249
Test name
Test status
Simulation time 97009577 ps
CPU time 2.54 seconds
Started May 02 02:49:38 PM PDT 24
Finished May 02 02:49:42 PM PDT 24
Peak memory 206752 kb
Host smart-35740ebd-0d45-408f-b69b-24ca84e83909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574851282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.574851282
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.812066719
Short name T227
Test name
Test status
Simulation time 112231172 ps
CPU time 0.86 seconds
Started May 02 02:48:48 PM PDT 24
Finished May 02 02:48:50 PM PDT 24
Peak memory 206332 kb
Host smart-2c9fcf3e-b9ca-4d58-a93b-5e4190a80472
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812066719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.812066719
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/2.edn_disable.2314606820
Short name T187
Test name
Test status
Simulation time 21942962 ps
CPU time 0.88 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 216068 kb
Host smart-8d356fa7-f632-4aa9-9328-5a3fc5cf8320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314606820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2314606820
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/31.edn_intr.538611926
Short name T29
Test name
Test status
Simulation time 57972823 ps
CPU time 0.85 seconds
Started May 02 02:52:41 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 215572 kb
Host smart-dcd4cc25-348f-41fc-bf57-9fbc0e8f24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538611926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.538611926
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/18.edn_disable.2693031588
Short name T183
Test name
Test status
Simulation time 163623455 ps
CPU time 0.85 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:17 PM PDT 24
Peak memory 216088 kb
Host smart-66b0ae61-5ab5-4eb9-8981-9c798fd90b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693031588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2693031588
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.2970237988
Short name T170
Test name
Test status
Simulation time 23520039 ps
CPU time 0.9 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:51:42 PM PDT 24
Peak memory 216236 kb
Host smart-1c28faae-7e8e-4750-bb2f-99021f80202d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970237988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2970237988
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/155.edn_genbits.3580592020
Short name T9
Test name
Test status
Simulation time 62766180 ps
CPU time 1.45 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 219752 kb
Host smart-3fb93fad-10f5-4604-bb59-a4c94dc28aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580592020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3580592020
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2853534241
Short name T19
Test name
Test status
Simulation time 80148614 ps
CPU time 1.54 seconds
Started May 02 02:54:05 PM PDT 24
Finished May 02 02:54:08 PM PDT 24
Peak memory 218316 kb
Host smart-a9f74928-fc97-43e8-8fef-5c0f9cb14159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853534241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2853534241
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.957634885
Short name T87
Test name
Test status
Simulation time 46322573 ps
CPU time 1.22 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 216824 kb
Host smart-d9df5caf-4c43-472f-8b2f-d27b28c1b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957634885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.957634885
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.1105266967
Short name T257
Test name
Test status
Simulation time 23649059 ps
CPU time 0.93 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 206940 kb
Host smart-4092daa2-46ca-4200-98b3-bfc93454fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105266967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1105266967
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_disable.3060341402
Short name T694
Test name
Test status
Simulation time 16532597 ps
CPU time 0.88 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 215240 kb
Host smart-76205c4e-07c1-4e56-b011-cd317a24cee3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060341402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3060341402
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4102151285
Short name T118
Test name
Test status
Simulation time 155613022 ps
CPU time 1.2 seconds
Started May 02 02:52:47 PM PDT 24
Finished May 02 02:52:49 PM PDT 24
Peak memory 216636 kb
Host smart-efbed1b2-abf1-4cce-bc28-5a62d2fcbc12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102151285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4102151285
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_intr.3509196287
Short name T32
Test name
Test status
Simulation time 26977425 ps
CPU time 0.91 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 215860 kb
Host smart-8b730c7a-f1f7-4d38-af20-2d14c0c65c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509196287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3509196287
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable.2426765613
Short name T175
Test name
Test status
Simulation time 11601298 ps
CPU time 0.88 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 216176 kb
Host smart-bcc01220-af3e-4f45-9b90-4976e650ff01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426765613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2426765613
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2797287573
Short name T102
Test name
Test status
Simulation time 75754476 ps
CPU time 1.1 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 216724 kb
Host smart-b0d5ce2f-e37c-4c1a-8937-7de51579fcc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797287573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2797287573
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3894816862
Short name T632
Test name
Test status
Simulation time 205514029 ps
CPU time 1.2 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 216776 kb
Host smart-467174cb-674f-4a12-b88c-e83c0d2ea842
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894816862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3894816862
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1479354065
Short name T386
Test name
Test status
Simulation time 73499259 ps
CPU time 1.2 seconds
Started May 02 02:52:09 PM PDT 24
Finished May 02 02:52:11 PM PDT 24
Peak memory 219452 kb
Host smart-14e35699-e43e-4e53-b523-329eddfa7254
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479354065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1479354065
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.2797525944
Short name T766
Test name
Test status
Simulation time 34984462 ps
CPU time 0.84 seconds
Started May 02 02:52:22 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 215972 kb
Host smart-123e2a90-a405-4cbc-8319-4880bc1ba6db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797525944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2797525944
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.309267953
Short name T668
Test name
Test status
Simulation time 40179365 ps
CPU time 1.38 seconds
Started May 02 02:52:26 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 216768 kb
Host smart-f543e509-720a-4ff0-afea-0aef92922fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309267953 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.309267953
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1455555826
Short name T120
Test name
Test status
Simulation time 30971207 ps
CPU time 1.13 seconds
Started May 02 02:52:34 PM PDT 24
Finished May 02 02:52:37 PM PDT 24
Peak memory 216568 kb
Host smart-e3c49420-e1a1-4f67-975f-54bf5e48aea5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455555826 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1455555826
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_disable.4270015293
Short name T147
Test name
Test status
Simulation time 22488134 ps
CPU time 0.9 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 216152 kb
Host smart-537352e4-23a7-4762-8f84-0f06f1728d09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270015293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4270015293
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/264.edn_genbits.163085385
Short name T41
Test name
Test status
Simulation time 170385040 ps
CPU time 2.28 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:29 PM PDT 24
Peak memory 218532 kb
Host smart-e53ff2d1-4caf-478b-af40-5d53ad14843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163085385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.163085385
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert_test.986712194
Short name T308
Test name
Test status
Simulation time 12453909 ps
CPU time 0.86 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 206496 kb
Host smart-f4e0b03c-5d73-45e2-8920-017a43aae82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986712194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.986712194
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_alert.2810973642
Short name T254
Test name
Test status
Simulation time 169696512 ps
CPU time 1.24 seconds
Started May 02 02:51:53 PM PDT 24
Finished May 02 02:51:56 PM PDT 24
Peak memory 215484 kb
Host smart-5b86a4da-78ca-4da6-8f57-06874e657f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810973642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2810973642
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3206768230
Short name T38
Test name
Test status
Simulation time 53258018 ps
CPU time 1.21 seconds
Started May 02 02:54:01 PM PDT 24
Finished May 02 02:54:04 PM PDT 24
Peak memory 216812 kb
Host smart-89289b48-784f-4ab0-8cc2-7432504b9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206768230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3206768230
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1110295391
Short name T222
Test name
Test status
Simulation time 21392018 ps
CPU time 0.81 seconds
Started May 02 02:48:43 PM PDT 24
Finished May 02 02:48:45 PM PDT 24
Peak memory 206320 kb
Host smart-2a7d2d24-a036-455b-8078-4e2f843c6e34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110295391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1110295391
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/278.edn_genbits.3479691174
Short name T673
Test name
Test status
Simulation time 84393674 ps
CPU time 1.7 seconds
Started May 02 02:54:26 PM PDT 24
Finished May 02 02:54:29 PM PDT 24
Peak memory 219548 kb
Host smart-dde2cb92-2068-4088-87e1-06a88a2687c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479691174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3479691174
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.421440077
Short name T263
Test name
Test status
Simulation time 24430221 ps
CPU time 1.06 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:29 PM PDT 24
Peak memory 206940 kb
Host smart-8a9fc43f-1e16-4a61-8782-ebffd562beba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421440077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.421440077
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/33.edn_genbits.2768128064
Short name T42
Test name
Test status
Simulation time 67708164 ps
CPU time 1.39 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:54 PM PDT 24
Peak memory 218260 kb
Host smart-346ce8c4-825d-411b-a13d-908c757855a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768128064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2768128064
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1589920897
Short name T95
Test name
Test status
Simulation time 23074789 ps
CPU time 0.98 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 02:51:48 PM PDT 24
Peak memory 215772 kb
Host smart-46518c7c-be4e-430a-b847-d4f2a7b5bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589920897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1589920897
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/67.edn_genbits.500642540
Short name T281
Test name
Test status
Simulation time 29892265 ps
CPU time 1.25 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 216980 kb
Host smart-372d95c9-beb5-4744-8727-2df76647b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500642540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.500642540
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.366083235
Short name T205
Test name
Test status
Simulation time 23327545 ps
CPU time 1.08 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:08 PM PDT 24
Peak memory 215476 kb
Host smart-ea35ea9e-f394-40b2-9f15-b145dec4d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366083235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.366083235
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1713573601
Short name T250
Test name
Test status
Simulation time 93730623 ps
CPU time 2.66 seconds
Started May 02 02:49:11 PM PDT 24
Finished May 02 02:49:15 PM PDT 24
Peak memory 206708 kb
Host smart-bc83a304-efec-4232-8f9c-ed3bfb331edd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713573601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1713573601
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.4289223087
Short name T22
Test name
Test status
Simulation time 25290830 ps
CPU time 0.93 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 206920 kb
Host smart-8886fb80-949c-4a2f-8f1d-5268dbe4eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289223087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4289223087
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/105.edn_genbits.2322057314
Short name T523
Test name
Test status
Simulation time 38726214 ps
CPU time 1.47 seconds
Started May 02 02:53:42 PM PDT 24
Finished May 02 02:53:45 PM PDT 24
Peak memory 218200 kb
Host smart-d2f6746f-a865-41b2-aa16-eeef1a30681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322057314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2322057314
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3696009900
Short name T278
Test name
Test status
Simulation time 72797150 ps
CPU time 1.47 seconds
Started May 02 02:53:49 PM PDT 24
Finished May 02 02:53:52 PM PDT 24
Peak memory 218232 kb
Host smart-da8e2d1c-a0c7-4eb9-b582-b3f6309d4bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696009900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3696009900
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3148764105
Short name T288
Test name
Test status
Simulation time 96695012 ps
CPU time 1.62 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:58 PM PDT 24
Peak memory 218436 kb
Host smart-4906ea2b-859a-409c-b08e-340b185ec4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148764105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3148764105
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1149983307
Short name T82
Test name
Test status
Simulation time 58438455 ps
CPU time 2.01 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:58 PM PDT 24
Peak memory 218240 kb
Host smart-71338dfd-6bab-4bca-a53b-4f36f9e9a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149983307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1149983307
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3769701950
Short name T677
Test name
Test status
Simulation time 78317597 ps
CPU time 1.19 seconds
Started May 02 02:51:59 PM PDT 24
Finished May 02 02:52:01 PM PDT 24
Peak memory 215544 kb
Host smart-2f01fb98-d0e1-429a-b2b1-2904c6564b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769701950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3769701950
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3159317479
Short name T272
Test name
Test status
Simulation time 52657995 ps
CPU time 1.01 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 217068 kb
Host smart-0ccbe50d-74c4-4ed4-8f3d-488348975197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159317479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3159317479
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.81315076
Short name T786
Test name
Test status
Simulation time 49951563 ps
CPU time 1.29 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 216956 kb
Host smart-e3eebf0c-9e6d-40be-a31e-9912af29d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81315076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.81315076
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1759692059
Short name T270
Test name
Test status
Simulation time 30118487 ps
CPU time 1.27 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:35 PM PDT 24
Peak memory 215624 kb
Host smart-4bf15cc6-58a5-4ae4-9839-54fcae243832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759692059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1759692059
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/42.edn_intr.3982781607
Short name T33
Test name
Test status
Simulation time 21917685 ps
CPU time 1.15 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:12 PM PDT 24
Peak memory 215808 kb
Host smart-e50943be-c68b-4839-8c8a-69250804fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982781607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3982781607
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.216580065
Short name T456
Test name
Test status
Simulation time 73972543 ps
CPU time 1.3 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:29 PM PDT 24
Peak memory 215588 kb
Host smart-8e20c5c0-78d2-4ea0-8e42-163dffefcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216580065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.216580065
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4229873756
Short name T232
Test name
Test status
Simulation time 78560540 ps
CPU time 1.56 seconds
Started May 02 02:48:51 PM PDT 24
Finished May 02 02:48:54 PM PDT 24
Peak memory 206372 kb
Host smart-aa395e76-b907-4873-af94-e6d0a2bcf772
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229873756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4229873756
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.355832076
Short name T909
Test name
Test status
Simulation time 60407137 ps
CPU time 3.36 seconds
Started May 02 02:48:44 PM PDT 24
Finished May 02 02:48:49 PM PDT 24
Peak memory 206428 kb
Host smart-1286dd15-e3db-4b95-8906-e0eb4594f09e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355832076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.355832076
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1776791265
Short name T953
Test name
Test status
Simulation time 50582302 ps
CPU time 1.26 seconds
Started May 02 02:48:50 PM PDT 24
Finished May 02 02:48:53 PM PDT 24
Peak memory 214616 kb
Host smart-2c0b1afa-a47f-4f3f-9a52-c23a505c43e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776791265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1776791265
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4265906900
Short name T942
Test name
Test status
Simulation time 15685130 ps
CPU time 0.86 seconds
Started May 02 02:48:46 PM PDT 24
Finished May 02 02:48:48 PM PDT 24
Peak memory 206208 kb
Host smart-2b4534cc-b893-4b75-a2c3-010d79e77769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265906900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4265906900
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3226083287
Short name T927
Test name
Test status
Simulation time 51604327 ps
CPU time 1.16 seconds
Started May 02 02:48:50 PM PDT 24
Finished May 02 02:48:53 PM PDT 24
Peak memory 206308 kb
Host smart-250f2be9-a968-40ad-aed0-a0db0fc586dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226083287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3226083287
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1167076897
Short name T890
Test name
Test status
Simulation time 81409000 ps
CPU time 2.88 seconds
Started May 02 02:48:46 PM PDT 24
Finished May 02 02:48:50 PM PDT 24
Peak memory 214568 kb
Host smart-2bf69d4d-61de-4667-9f53-b4e95eb9e1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167076897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1167076897
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1459649239
Short name T903
Test name
Test status
Simulation time 229051941 ps
CPU time 4.46 seconds
Started May 02 02:48:47 PM PDT 24
Finished May 02 02:48:53 PM PDT 24
Peak memory 206420 kb
Host smart-1c3b04cc-b773-4257-8c57-6a46291e63e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459649239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1459649239
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2499887179
Short name T967
Test name
Test status
Simulation time 76486909 ps
CPU time 1.1 seconds
Started May 02 02:48:58 PM PDT 24
Finished May 02 02:49:01 PM PDT 24
Peak memory 206344 kb
Host smart-dbcd0779-2203-4ccb-9e2b-e455043c6068
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499887179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2499887179
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2869658724
Short name T908
Test name
Test status
Simulation time 358125329 ps
CPU time 5.35 seconds
Started May 02 02:48:57 PM PDT 24
Finished May 02 02:49:04 PM PDT 24
Peak memory 206276 kb
Host smart-64069d59-526d-4fa1-ae61-66b064d1e6a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869658724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2869658724
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2548977398
Short name T226
Test name
Test status
Simulation time 56151944 ps
CPU time 0.86 seconds
Started May 02 02:48:50 PM PDT 24
Finished May 02 02:48:53 PM PDT 24
Peak memory 206332 kb
Host smart-93ffd921-0cfa-4fd7-a240-1592ac9eecdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548977398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2548977398
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3494392254
Short name T970
Test name
Test status
Simulation time 104138437 ps
CPU time 1.03 seconds
Started May 02 02:48:57 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 215648 kb
Host smart-8aac2218-3b57-4319-a483-75977a1f678e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494392254 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3494392254
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.83651958
Short name T911
Test name
Test status
Simulation time 17637876 ps
CPU time 0.81 seconds
Started May 02 02:48:58 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 206140 kb
Host smart-9ad8d73d-8ea2-4491-85ab-ae396a64496c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83651958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.83651958
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1684826991
Short name T858
Test name
Test status
Simulation time 44544851 ps
CPU time 0.87 seconds
Started May 02 02:48:50 PM PDT 24
Finished May 02 02:48:52 PM PDT 24
Peak memory 206232 kb
Host smart-c2dd7711-866a-48b8-b733-4a291a5a36fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684826991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1684826991
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.716415045
Short name T921
Test name
Test status
Simulation time 41867883 ps
CPU time 1.24 seconds
Started May 02 02:48:57 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 206356 kb
Host smart-1b6aa57d-708a-4b19-8e84-b0131992f4c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716415045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.716415045
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3950574423
Short name T912
Test name
Test status
Simulation time 75311549 ps
CPU time 2.65 seconds
Started May 02 02:48:51 PM PDT 24
Finished May 02 02:48:55 PM PDT 24
Peak memory 214604 kb
Host smart-5e542ff9-5fb7-44cd-9cdc-34b8b2d5051e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950574423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3950574423
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3846952846
Short name T961
Test name
Test status
Simulation time 519523033 ps
CPU time 2.35 seconds
Started May 02 02:48:50 PM PDT 24
Finished May 02 02:48:54 PM PDT 24
Peak memory 206388 kb
Host smart-520d84e7-1c43-4129-91aa-d7adc53b4e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846952846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3846952846
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3148572180
Short name T887
Test name
Test status
Simulation time 97073801 ps
CPU time 1.36 seconds
Started May 02 02:49:38 PM PDT 24
Finished May 02 02:49:40 PM PDT 24
Peak memory 214628 kb
Host smart-30956bc0-57f4-478c-9b5c-e4bbed858354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148572180 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3148572180
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2497753658
Short name T937
Test name
Test status
Simulation time 16320105 ps
CPU time 0.95 seconds
Started May 02 02:49:41 PM PDT 24
Finished May 02 02:49:43 PM PDT 24
Peak memory 206300 kb
Host smart-aabffdfd-8924-42c5-8634-9ce1f016d9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497753658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2497753658
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2884323070
Short name T925
Test name
Test status
Simulation time 13758565 ps
CPU time 0.87 seconds
Started May 02 02:49:37 PM PDT 24
Finished May 02 02:49:39 PM PDT 24
Peak memory 206220 kb
Host smart-df1c17fc-11a8-4b07-ae99-a05575593d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884323070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2884323070
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.334032954
Short name T916
Test name
Test status
Simulation time 105925225 ps
CPU time 1.2 seconds
Started May 02 02:49:37 PM PDT 24
Finished May 02 02:49:40 PM PDT 24
Peak memory 206260 kb
Host smart-ae7d9e8a-9511-4e33-be2e-5355934dc08d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334032954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.334032954
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2788186906
Short name T843
Test name
Test status
Simulation time 40300327 ps
CPU time 1.48 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 214500 kb
Host smart-40546f14-aa44-48e7-ae89-83abaf06b1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788186906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2788186906
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2608923062
Short name T922
Test name
Test status
Simulation time 843328634 ps
CPU time 1.58 seconds
Started May 02 02:49:38 PM PDT 24
Finished May 02 02:49:41 PM PDT 24
Peak memory 206368 kb
Host smart-ae0e2bed-de27-4c96-be39-a6c866341f53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608923062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2608923062
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.406734674
Short name T958
Test name
Test status
Simulation time 21306129 ps
CPU time 1.51 seconds
Started May 02 02:49:36 PM PDT 24
Finished May 02 02:49:39 PM PDT 24
Peak memory 214652 kb
Host smart-c13d45e3-a5a8-4ab6-b4b1-f7b7fed69ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406734674 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.406734674
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4013505398
Short name T930
Test name
Test status
Simulation time 22159757 ps
CPU time 0.84 seconds
Started May 02 02:49:37 PM PDT 24
Finished May 02 02:49:39 PM PDT 24
Peak memory 206324 kb
Host smart-184f5a61-3329-4936-bba4-0a78bbb4f18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013505398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4013505398
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2818314794
Short name T963
Test name
Test status
Simulation time 124909571 ps
CPU time 0.88 seconds
Started May 02 02:49:37 PM PDT 24
Finished May 02 02:49:39 PM PDT 24
Peak memory 206184 kb
Host smart-2b9bbdb7-6028-4d48-a134-4d553722febe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818314794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2818314794
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3480403464
Short name T239
Test name
Test status
Simulation time 19696534 ps
CPU time 1.16 seconds
Started May 02 02:49:35 PM PDT 24
Finished May 02 02:49:38 PM PDT 24
Peak memory 206408 kb
Host smart-0b27b274-3a31-4351-85fe-7f5033a6bd10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480403464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3480403464
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.858737146
Short name T934
Test name
Test status
Simulation time 194432755 ps
CPU time 3.6 seconds
Started May 02 02:49:37 PM PDT 24
Finished May 02 02:49:42 PM PDT 24
Peak memory 214540 kb
Host smart-8cf2e4b8-bda2-4500-a11f-cda2a71ded98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858737146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.858737146
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1590856550
Short name T874
Test name
Test status
Simulation time 57541147 ps
CPU time 1.11 seconds
Started May 02 02:49:41 PM PDT 24
Finished May 02 02:49:43 PM PDT 24
Peak memory 214644 kb
Host smart-44cdad72-9008-4a4d-b7b3-5a9842a6e724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590856550 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1590856550
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2046737719
Short name T223
Test name
Test status
Simulation time 58251232 ps
CPU time 0.88 seconds
Started May 02 02:49:42 PM PDT 24
Finished May 02 02:49:44 PM PDT 24
Peak memory 206020 kb
Host smart-c9dfe683-bbc0-403f-899a-4b47f2da496a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046737719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2046737719
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2158890562
Short name T964
Test name
Test status
Simulation time 15110925 ps
CPU time 0.9 seconds
Started May 02 02:49:38 PM PDT 24
Finished May 02 02:49:40 PM PDT 24
Peak memory 206228 kb
Host smart-cf63586e-c0ad-4adf-94cd-b7d0ab8b54ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158890562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2158890562
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1548664391
Short name T897
Test name
Test status
Simulation time 21921734 ps
CPU time 1.06 seconds
Started May 02 02:49:42 PM PDT 24
Finished May 02 02:49:44 PM PDT 24
Peak memory 206356 kb
Host smart-8ed76cba-8ad8-452d-a501-befaac811def
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548664391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1548664391
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3879411292
Short name T940
Test name
Test status
Simulation time 25610388 ps
CPU time 1.43 seconds
Started May 02 02:49:39 PM PDT 24
Finished May 02 02:49:41 PM PDT 24
Peak memory 214436 kb
Host smart-a3d60363-2f0e-4509-811c-0a0c66d686ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879411292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3879411292
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.202075211
Short name T245
Test name
Test status
Simulation time 554542044 ps
CPU time 2.15 seconds
Started May 02 02:49:38 PM PDT 24
Finished May 02 02:49:42 PM PDT 24
Peak memory 206368 kb
Host smart-e382f7d7-a24e-43b3-b998-8c51362cebc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202075211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.202075211
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3606781664
Short name T860
Test name
Test status
Simulation time 27646044 ps
CPU time 0.93 seconds
Started May 02 02:49:42 PM PDT 24
Finished May 02 02:49:44 PM PDT 24
Peak memory 206240 kb
Host smart-181c3e31-9774-4f34-92b8-0b59b1d77aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606781664 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3606781664
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.139090203
Short name T230
Test name
Test status
Simulation time 10823943 ps
CPU time 0.84 seconds
Started May 02 02:49:43 PM PDT 24
Finished May 02 02:49:44 PM PDT 24
Peak memory 206344 kb
Host smart-097b7d40-f396-4eb1-9730-1b35277b2e11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139090203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.139090203
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2874472677
Short name T915
Test name
Test status
Simulation time 60409386 ps
CPU time 0.81 seconds
Started May 02 02:49:43 PM PDT 24
Finished May 02 02:49:45 PM PDT 24
Peak memory 206156 kb
Host smart-c248f105-0d41-4e31-ab98-4376c8720194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874472677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2874472677
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3197790237
Short name T932
Test name
Test status
Simulation time 68844185 ps
CPU time 0.95 seconds
Started May 02 02:49:44 PM PDT 24
Finished May 02 02:49:46 PM PDT 24
Peak memory 206300 kb
Host smart-7af4e9c9-86f8-4792-acbf-e99fcc9b7d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197790237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3197790237
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.896059235
Short name T969
Test name
Test status
Simulation time 110211121 ps
CPU time 2.67 seconds
Started May 02 02:49:43 PM PDT 24
Finished May 02 02:49:46 PM PDT 24
Peak memory 214592 kb
Host smart-45bc0018-c181-4b1f-9d75-d85449dece0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896059235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.896059235
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2647751771
Short name T966
Test name
Test status
Simulation time 85648162 ps
CPU time 1.61 seconds
Started May 02 02:49:43 PM PDT 24
Finished May 02 02:49:46 PM PDT 24
Peak memory 214552 kb
Host smart-aaaf23b2-e9b1-42ca-bfc2-11637474c6e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647751771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2647751771
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3190124855
Short name T895
Test name
Test status
Simulation time 63501733 ps
CPU time 1 seconds
Started May 02 02:49:48 PM PDT 24
Finished May 02 02:49:50 PM PDT 24
Peak memory 215712 kb
Host smart-df69b2f3-b920-430a-b1d8-6c6d376ee523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190124855 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3190124855
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4193584606
Short name T948
Test name
Test status
Simulation time 11385559 ps
CPU time 0.84 seconds
Started May 02 02:49:50 PM PDT 24
Finished May 02 02:49:52 PM PDT 24
Peak memory 206284 kb
Host smart-25194dec-c829-4edb-9650-a45d6521fa54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193584606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4193584606
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.69117898
Short name T924
Test name
Test status
Simulation time 37916610 ps
CPU time 0.82 seconds
Started May 02 02:49:43 PM PDT 24
Finished May 02 02:49:45 PM PDT 24
Peak memory 206020 kb
Host smart-6c028f17-44df-4206-bbb0-4c6213ac6517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69117898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.69117898
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1524393028
Short name T900
Test name
Test status
Simulation time 23197228 ps
CPU time 0.92 seconds
Started May 02 02:49:51 PM PDT 24
Finished May 02 02:49:53 PM PDT 24
Peak memory 206388 kb
Host smart-4d7c46e5-ee0f-4735-83f9-4c606c3badac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524393028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1524393028
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1048840301
Short name T871
Test name
Test status
Simulation time 223350184 ps
CPU time 3.6 seconds
Started May 02 02:49:46 PM PDT 24
Finished May 02 02:49:51 PM PDT 24
Peak memory 214564 kb
Host smart-a4d1393d-6fff-4d87-a0fe-6b28389a2a54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048840301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1048840301
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3628047505
Short name T252
Test name
Test status
Simulation time 101395442 ps
CPU time 2.63 seconds
Started May 02 02:49:42 PM PDT 24
Finished May 02 02:49:46 PM PDT 24
Peak memory 206400 kb
Host smart-425f6de5-88af-4528-9100-f4ea9d455fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628047505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3628047505
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.410941497
Short name T848
Test name
Test status
Simulation time 41015464 ps
CPU time 1.54 seconds
Started May 02 02:49:48 PM PDT 24
Finished May 02 02:49:51 PM PDT 24
Peak memory 214572 kb
Host smart-22db9806-3592-4ed3-88e8-bbdbc5348be5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410941497 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.410941497
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2481862817
Short name T225
Test name
Test status
Simulation time 49214340 ps
CPU time 0.94 seconds
Started May 02 02:49:51 PM PDT 24
Finished May 02 02:49:53 PM PDT 24
Peak memory 206188 kb
Host smart-944c3f4a-f8d0-462c-904c-019daa7f8885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481862817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2481862817
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3546471679
Short name T866
Test name
Test status
Simulation time 14142529 ps
CPU time 0.91 seconds
Started May 02 02:49:53 PM PDT 24
Finished May 02 02:49:55 PM PDT 24
Peak memory 206184 kb
Host smart-880abedd-6961-408d-b515-201ba70d1d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546471679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3546471679
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4145369486
Short name T238
Test name
Test status
Simulation time 64195147 ps
CPU time 1.05 seconds
Started May 02 02:49:53 PM PDT 24
Finished May 02 02:49:55 PM PDT 24
Peak memory 206360 kb
Host smart-6a9bf39b-deb9-454e-87d9-2f4c02c696bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145369486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4145369486
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3705293445
Short name T914
Test name
Test status
Simulation time 132942899 ps
CPU time 2.2 seconds
Started May 02 02:49:49 PM PDT 24
Finished May 02 02:49:52 PM PDT 24
Peak memory 214580 kb
Host smart-1afbf811-3479-4b7f-9824-2fa2fca939e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705293445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3705293445
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.621556151
Short name T243
Test name
Test status
Simulation time 143964978 ps
CPU time 2 seconds
Started May 02 02:49:51 PM PDT 24
Finished May 02 02:49:54 PM PDT 24
Peak memory 206340 kb
Host smart-0e9c56ba-f756-46b8-96e3-cfbc592e5838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621556151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.621556151
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.16591908
Short name T901
Test name
Test status
Simulation time 39719804 ps
CPU time 1.6 seconds
Started May 02 02:49:58 PM PDT 24
Finished May 02 02:50:01 PM PDT 24
Peak memory 214624 kb
Host smart-82ec9955-660c-46d7-b093-4eafa95d6639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591908 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.16591908
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3548902179
Short name T929
Test name
Test status
Simulation time 45411521 ps
CPU time 0.76 seconds
Started May 02 02:49:56 PM PDT 24
Finished May 02 02:49:58 PM PDT 24
Peak memory 206048 kb
Host smart-d52764e2-c187-4b54-b331-e2272f1f267e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548902179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3548902179
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2149608807
Short name T863
Test name
Test status
Simulation time 11020589 ps
CPU time 0.83 seconds
Started May 02 02:49:50 PM PDT 24
Finished May 02 02:49:52 PM PDT 24
Peak memory 206220 kb
Host smart-310c0d07-b25e-4d94-a616-31c6b45053c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149608807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2149608807
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4230415908
Short name T221
Test name
Test status
Simulation time 43838058 ps
CPU time 1.41 seconds
Started May 02 02:49:58 PM PDT 24
Finished May 02 02:50:01 PM PDT 24
Peak memory 206336 kb
Host smart-105103c3-e206-4f54-b859-d785c9e468bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230415908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4230415908
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2115390489
Short name T928
Test name
Test status
Simulation time 85393354 ps
CPU time 2.01 seconds
Started May 02 02:49:49 PM PDT 24
Finished May 02 02:49:52 PM PDT 24
Peak memory 214448 kb
Host smart-408e8600-6965-471f-9007-cd3a23fff841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115390489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2115390489
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3988838795
Short name T902
Test name
Test status
Simulation time 373297099 ps
CPU time 1.77 seconds
Started May 02 02:49:50 PM PDT 24
Finished May 02 02:49:52 PM PDT 24
Peak memory 206424 kb
Host smart-b1ecb35d-7929-4be3-932c-3a9bdb07750e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988838795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3988838795
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1099459998
Short name T893
Test name
Test status
Simulation time 74550856 ps
CPU time 1.1 seconds
Started May 02 02:49:56 PM PDT 24
Finished May 02 02:49:59 PM PDT 24
Peak memory 214724 kb
Host smart-924ffb1b-75e7-4330-9490-0e3b93b2cde5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099459998 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1099459998
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2056593572
Short name T242
Test name
Test status
Simulation time 48952973 ps
CPU time 0.92 seconds
Started May 02 02:49:55 PM PDT 24
Finished May 02 02:49:57 PM PDT 24
Peak memory 206284 kb
Host smart-fe72d4c6-734f-417e-962f-00c32ba089a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056593572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2056593572
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1283109228
Short name T960
Test name
Test status
Simulation time 34220467 ps
CPU time 0.88 seconds
Started May 02 02:49:54 PM PDT 24
Finished May 02 02:49:56 PM PDT 24
Peak memory 206212 kb
Host smart-9b18f737-f42f-4a21-9252-894737d8e589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283109228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1283109228
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2926890411
Short name T943
Test name
Test status
Simulation time 22338695 ps
CPU time 0.98 seconds
Started May 02 02:49:54 PM PDT 24
Finished May 02 02:49:56 PM PDT 24
Peak memory 206332 kb
Host smart-a8d769bf-fb8c-4201-880e-29f85790a1df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926890411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2926890411
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.679393818
Short name T859
Test name
Test status
Simulation time 42397131 ps
CPU time 2.71 seconds
Started May 02 02:49:55 PM PDT 24
Finished May 02 02:49:59 PM PDT 24
Peak memory 214508 kb
Host smart-ef909a1f-5a87-4955-be23-8fe1bf5e4ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679393818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.679393818
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2304377094
Short name T244
Test name
Test status
Simulation time 102212956 ps
CPU time 2.59 seconds
Started May 02 02:49:56 PM PDT 24
Finished May 02 02:50:00 PM PDT 24
Peak memory 206344 kb
Host smart-9bde94b5-b0c5-4328-a6d0-5f8e0b428ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304377094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2304377094
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3252643400
Short name T955
Test name
Test status
Simulation time 22569735 ps
CPU time 1.65 seconds
Started May 02 02:50:00 PM PDT 24
Finished May 02 02:50:03 PM PDT 24
Peak memory 214576 kb
Host smart-2e750359-e8d3-4fe6-86cc-b90467b20ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252643400 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3252643400
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2775975752
Short name T892
Test name
Test status
Simulation time 85680510 ps
CPU time 0.81 seconds
Started May 02 02:49:54 PM PDT 24
Finished May 02 02:49:56 PM PDT 24
Peak memory 206048 kb
Host smart-f2839b69-72d7-4aa9-9fb8-c7a7faf3bc3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775975752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2775975752
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3994327052
Short name T852
Test name
Test status
Simulation time 28570346 ps
CPU time 0.88 seconds
Started May 02 02:49:54 PM PDT 24
Finished May 02 02:49:56 PM PDT 24
Peak memory 206208 kb
Host smart-a144326e-2c44-4455-88f5-4332d2020549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994327052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3994327052
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.447340046
Short name T938
Test name
Test status
Simulation time 55660097 ps
CPU time 1.11 seconds
Started May 02 02:50:01 PM PDT 24
Finished May 02 02:50:03 PM PDT 24
Peak memory 206388 kb
Host smart-379d2bd9-14b0-4a1a-a06b-38fbd78af0dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447340046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.447340046
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1484507765
Short name T965
Test name
Test status
Simulation time 287195417 ps
CPU time 4.74 seconds
Started May 02 02:49:55 PM PDT 24
Finished May 02 02:50:01 PM PDT 24
Peak memory 214524 kb
Host smart-ab425158-5894-463b-b9a5-2c72aabfb528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484507765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1484507765
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3867334557
Short name T905
Test name
Test status
Simulation time 88599579 ps
CPU time 2.51 seconds
Started May 02 02:49:54 PM PDT 24
Finished May 02 02:49:57 PM PDT 24
Peak memory 206588 kb
Host smart-cc2bd8fe-77da-420f-847b-a0f04d4c5184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867334557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3867334557
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.297194979
Short name T850
Test name
Test status
Simulation time 16719397 ps
CPU time 1.14 seconds
Started May 02 02:50:05 PM PDT 24
Finished May 02 02:50:08 PM PDT 24
Peak memory 214692 kb
Host smart-f0ec003b-1347-4c3a-9a02-6242ea7587a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297194979 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.297194979
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3275586740
Short name T234
Test name
Test status
Simulation time 45193203 ps
CPU time 0.82 seconds
Started May 02 02:50:01 PM PDT 24
Finished May 02 02:50:03 PM PDT 24
Peak memory 206048 kb
Host smart-97303944-837a-4025-a13b-59dea757b97c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275586740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3275586740
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2250281598
Short name T906
Test name
Test status
Simulation time 15612713 ps
CPU time 0.92 seconds
Started May 02 02:50:01 PM PDT 24
Finished May 02 02:50:03 PM PDT 24
Peak memory 206288 kb
Host smart-f881fbf6-18e4-4393-9666-8f521786048d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250281598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2250281598
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3719039703
Short name T886
Test name
Test status
Simulation time 22085824 ps
CPU time 1.16 seconds
Started May 02 02:50:05 PM PDT 24
Finished May 02 02:50:07 PM PDT 24
Peak memory 206364 kb
Host smart-e885cba2-9281-4572-8ba4-d5afbf445a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719039703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3719039703
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3616279965
Short name T933
Test name
Test status
Simulation time 127745576 ps
CPU time 2.58 seconds
Started May 02 02:50:02 PM PDT 24
Finished May 02 02:50:06 PM PDT 24
Peak memory 214556 kb
Host smart-4421311f-98a3-4366-abcb-9ebe23b4d28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616279965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3616279965
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1641162019
Short name T251
Test name
Test status
Simulation time 102195363 ps
CPU time 2.56 seconds
Started May 02 02:50:01 PM PDT 24
Finished May 02 02:50:05 PM PDT 24
Peak memory 214536 kb
Host smart-99fe30f9-ac3c-4814-872e-bbcd91e6ebe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641162019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1641162019
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1235746050
Short name T220
Test name
Test status
Simulation time 49250306 ps
CPU time 1.2 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 206332 kb
Host smart-fc4f273c-6e5a-473c-b557-fdb9bae24a52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235746050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1235746050
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.4294354176
Short name T235
Test name
Test status
Simulation time 268019624 ps
CPU time 3.42 seconds
Started May 02 02:49:03 PM PDT 24
Finished May 02 02:49:08 PM PDT 24
Peak memory 206260 kb
Host smart-92f55e67-c660-4565-9dca-337525b90ea3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294354176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4294354176
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1273588486
Short name T910
Test name
Test status
Simulation time 32456334 ps
CPU time 1 seconds
Started May 02 02:48:57 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 206260 kb
Host smart-7f039354-22a6-4e22-b8fc-fb076bf09ffb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273588486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1273588486
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2490658857
Short name T845
Test name
Test status
Simulation time 40188132 ps
CPU time 1.32 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 214628 kb
Host smart-f894d7d1-2fcb-4579-a7ea-2d00f5324783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490658857 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2490658857
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.192967587
Short name T237
Test name
Test status
Simulation time 31189092 ps
CPU time 0.78 seconds
Started May 02 02:48:57 PM PDT 24
Finished May 02 02:48:59 PM PDT 24
Peak memory 206140 kb
Host smart-52ae428d-c175-4c36-a441-8b0d7bf8fcd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192967587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.192967587
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.927067428
Short name T861
Test name
Test status
Simulation time 21108565 ps
CPU time 0.86 seconds
Started May 02 02:48:58 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 206184 kb
Host smart-11aed8ef-9afd-4891-b642-adeb8232e40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927067428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.927067428
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4092053677
Short name T219
Test name
Test status
Simulation time 41745348 ps
CPU time 1.06 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 206308 kb
Host smart-946e7e17-bc77-47b1-8fc7-db93b47c4ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092053677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4092053677
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.613821254
Short name T947
Test name
Test status
Simulation time 112973690 ps
CPU time 3.66 seconds
Started May 02 02:48:58 PM PDT 24
Finished May 02 02:49:03 PM PDT 24
Peak memory 214536 kb
Host smart-f3018570-113c-43fb-960d-f6963fc10354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613821254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.613821254
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1612396944
Short name T885
Test name
Test status
Simulation time 158121872 ps
CPU time 2.35 seconds
Started May 02 02:48:56 PM PDT 24
Finished May 02 02:49:00 PM PDT 24
Peak memory 206428 kb
Host smart-c181c67c-a0df-4171-8391-2c6eb75169a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612396944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1612396944
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3083527658
Short name T867
Test name
Test status
Simulation time 17484487 ps
CPU time 0.83 seconds
Started May 02 02:50:03 PM PDT 24
Finished May 02 02:50:04 PM PDT 24
Peak memory 206008 kb
Host smart-8a8b66cc-6b41-4989-9044-c1e3fd6f740d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083527658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3083527658
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1932249269
Short name T873
Test name
Test status
Simulation time 42209861 ps
CPU time 0.85 seconds
Started May 02 02:50:01 PM PDT 24
Finished May 02 02:50:03 PM PDT 24
Peak memory 206220 kb
Host smart-fa348602-d16e-478e-92d5-3b562f9de217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932249269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1932249269
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2028605176
Short name T973
Test name
Test status
Simulation time 13038609 ps
CPU time 0.84 seconds
Started May 02 02:50:10 PM PDT 24
Finished May 02 02:50:13 PM PDT 24
Peak memory 206216 kb
Host smart-9fb4921b-21a5-418d-8440-c5c6ea2fbcda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028605176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2028605176
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3036310994
Short name T945
Test name
Test status
Simulation time 41871403 ps
CPU time 0.88 seconds
Started May 02 02:50:13 PM PDT 24
Finished May 02 02:50:16 PM PDT 24
Peak memory 206200 kb
Host smart-d5372509-b57c-4141-a6f2-778c4c375cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036310994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3036310994
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1805131668
Short name T971
Test name
Test status
Simulation time 27997607 ps
CPU time 0.89 seconds
Started May 02 02:50:09 PM PDT 24
Finished May 02 02:50:12 PM PDT 24
Peak memory 206164 kb
Host smart-91f9f7db-7b23-408c-ad34-0f85eaaf248c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805131668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1805131668
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2418483358
Short name T849
Test name
Test status
Simulation time 11142787 ps
CPU time 0.83 seconds
Started May 02 02:50:11 PM PDT 24
Finished May 02 02:50:14 PM PDT 24
Peak memory 206220 kb
Host smart-e2258fb7-e849-401a-824d-395ce0adb453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418483358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2418483358
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2671054802
Short name T956
Test name
Test status
Simulation time 71756679 ps
CPU time 0.82 seconds
Started May 02 02:50:09 PM PDT 24
Finished May 02 02:50:12 PM PDT 24
Peak memory 206236 kb
Host smart-70dc1bf8-05cb-4960-bb3a-a59d6f12bbea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671054802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2671054802
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.353770292
Short name T857
Test name
Test status
Simulation time 11881848 ps
CPU time 0.85 seconds
Started May 02 02:50:07 PM PDT 24
Finished May 02 02:50:09 PM PDT 24
Peak memory 206180 kb
Host smart-f12555f0-8f2d-44bb-8d95-6acc47ff0632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353770292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.353770292
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2847982535
Short name T877
Test name
Test status
Simulation time 36745804 ps
CPU time 0.86 seconds
Started May 02 02:50:13 PM PDT 24
Finished May 02 02:50:16 PM PDT 24
Peak memory 205912 kb
Host smart-6aa2e8d0-2dfd-4e73-bce6-8925a1af477d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847982535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2847982535
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2488014862
Short name T878
Test name
Test status
Simulation time 24337317 ps
CPU time 0.85 seconds
Started May 02 02:50:12 PM PDT 24
Finished May 02 02:50:15 PM PDT 24
Peak memory 206184 kb
Host smart-00599cf4-d163-4348-a02e-1c45c034a659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488014862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2488014862
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2764195635
Short name T236
Test name
Test status
Simulation time 19135966 ps
CPU time 1.27 seconds
Started May 02 02:49:10 PM PDT 24
Finished May 02 02:49:12 PM PDT 24
Peak memory 206288 kb
Host smart-28d2dff9-4337-4735-8da4-6185ce563e69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764195635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2764195635
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3584048729
Short name T952
Test name
Test status
Simulation time 34887043 ps
CPU time 2.03 seconds
Started May 02 02:49:03 PM PDT 24
Finished May 02 02:49:06 PM PDT 24
Peak memory 206304 kb
Host smart-56056595-21b6-43b1-9482-ed887c6f57f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584048729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3584048729
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.191410045
Short name T231
Test name
Test status
Simulation time 31167576 ps
CPU time 0.91 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:06 PM PDT 24
Peak memory 206348 kb
Host smart-a6302d5d-d23d-4b07-968b-a05a92d0cfd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191410045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.191410045
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1720229168
Short name T894
Test name
Test status
Simulation time 55435236 ps
CPU time 1.76 seconds
Started May 02 02:49:12 PM PDT 24
Finished May 02 02:49:16 PM PDT 24
Peak memory 214588 kb
Host smart-b8b7d06e-77b1-468c-aa8c-1928974cf1fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720229168 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1720229168
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1336816033
Short name T228
Test name
Test status
Simulation time 54595018 ps
CPU time 0.95 seconds
Started May 02 02:49:05 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 206376 kb
Host smart-8755ff8e-4d68-4061-a46f-27188cdb6136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336816033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1336816033
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3917756854
Short name T974
Test name
Test status
Simulation time 14788681 ps
CPU time 0.93 seconds
Started May 02 02:49:05 PM PDT 24
Finished May 02 02:49:08 PM PDT 24
Peak memory 206228 kb
Host smart-7cd3c49f-3af3-4278-a241-bc1e3e4e3e60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917756854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3917756854
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2739376803
Short name T868
Test name
Test status
Simulation time 44237446 ps
CPU time 0.92 seconds
Started May 02 02:49:11 PM PDT 24
Finished May 02 02:49:13 PM PDT 24
Peak memory 206292 kb
Host smart-f65d3e76-372e-4d47-8751-6997ee8d7587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739376803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2739376803
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.549246348
Short name T936
Test name
Test status
Simulation time 46090668 ps
CPU time 1.75 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 214588 kb
Host smart-f8ae8226-0632-4301-94a1-15411d3f6c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549246348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.549246348
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4094986518
Short name T968
Test name
Test status
Simulation time 155214540 ps
CPU time 1.64 seconds
Started May 02 02:49:04 PM PDT 24
Finished May 02 02:49:07 PM PDT 24
Peak memory 206504 kb
Host smart-1b53c9b5-1997-4462-be3e-f942889f4ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094986518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4094986518
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.243909906
Short name T842
Test name
Test status
Simulation time 52879082 ps
CPU time 0.8 seconds
Started May 02 02:50:10 PM PDT 24
Finished May 02 02:50:13 PM PDT 24
Peak memory 206228 kb
Host smart-d6a58285-e814-4d21-87ba-c35a3475131c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243909906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.243909906
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1929669323
Short name T946
Test name
Test status
Simulation time 18760079 ps
CPU time 0.79 seconds
Started May 02 02:50:10 PM PDT 24
Finished May 02 02:50:13 PM PDT 24
Peak memory 206208 kb
Host smart-6b7de106-e161-4019-b1ee-7176165d023d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929669323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1929669323
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3352214046
Short name T864
Test name
Test status
Simulation time 21479630 ps
CPU time 0.83 seconds
Started May 02 02:50:08 PM PDT 24
Finished May 02 02:50:10 PM PDT 24
Peak memory 206220 kb
Host smart-7f031d1a-7294-428c-b938-86832de4cfdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352214046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3352214046
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1948100984
Short name T862
Test name
Test status
Simulation time 16609787 ps
CPU time 0.93 seconds
Started May 02 02:50:12 PM PDT 24
Finished May 02 02:50:15 PM PDT 24
Peak memory 206276 kb
Host smart-50742ed1-5e9f-4991-8b0e-5830f7c6bee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948100984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1948100984
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.597349457
Short name T865
Test name
Test status
Simulation time 12704948 ps
CPU time 0.83 seconds
Started May 02 02:50:10 PM PDT 24
Finished May 02 02:50:14 PM PDT 24
Peak memory 206184 kb
Host smart-39246929-7919-4771-92d7-26aedba7f924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597349457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.597349457
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1087489186
Short name T853
Test name
Test status
Simulation time 15146902 ps
CPU time 0.91 seconds
Started May 02 02:50:09 PM PDT 24
Finished May 02 02:50:13 PM PDT 24
Peak memory 206160 kb
Host smart-93d4b0a4-bd4f-4c7c-973c-ccaec4be5811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087489186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1087489186
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3217839713
Short name T847
Test name
Test status
Simulation time 101390267 ps
CPU time 0.81 seconds
Started May 02 02:50:08 PM PDT 24
Finished May 02 02:50:11 PM PDT 24
Peak memory 205928 kb
Host smart-e60f5bf2-27ad-4a39-9795-15670f25b209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217839713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3217839713
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4179498333
Short name T972
Test name
Test status
Simulation time 57474709 ps
CPU time 0.89 seconds
Started May 02 02:50:09 PM PDT 24
Finished May 02 02:50:13 PM PDT 24
Peak memory 206228 kb
Host smart-32c9272f-b0f9-4daa-ba40-f74039539a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179498333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4179498333
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3307410517
Short name T844
Test name
Test status
Simulation time 30219363 ps
CPU time 0.84 seconds
Started May 02 02:50:08 PM PDT 24
Finished May 02 02:50:11 PM PDT 24
Peak memory 206240 kb
Host smart-d3d2052c-dee5-4d21-8413-7bc6ff1bdcf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307410517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3307410517
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2252488283
Short name T957
Test name
Test status
Simulation time 14914315 ps
CPU time 0.92 seconds
Started May 02 02:50:08 PM PDT 24
Finished May 02 02:50:11 PM PDT 24
Peak memory 206172 kb
Host smart-ad973dc5-07ae-470b-ab14-2093d4e39c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252488283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2252488283
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.864943458
Short name T224
Test name
Test status
Simulation time 41029259 ps
CPU time 1.47 seconds
Started May 02 02:49:17 PM PDT 24
Finished May 02 02:49:21 PM PDT 24
Peak memory 206352 kb
Host smart-af1eddc4-ca66-4fcd-8714-4e9d30b0e666
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864943458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.864943458
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.505153759
Short name T941
Test name
Test status
Simulation time 131344045 ps
CPU time 3.52 seconds
Started May 02 02:49:18 PM PDT 24
Finished May 02 02:49:23 PM PDT 24
Peak memory 206272 kb
Host smart-1783d1c0-e49d-49ca-972c-0a2330540c56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505153759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.505153759
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2870225822
Short name T931
Test name
Test status
Simulation time 24478406 ps
CPU time 0.97 seconds
Started May 02 02:49:11 PM PDT 24
Finished May 02 02:49:14 PM PDT 24
Peak memory 206208 kb
Host smart-9479d94e-2347-48e8-9c74-b541b15e433e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870225822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2870225822
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2733093546
Short name T846
Test name
Test status
Simulation time 264916962 ps
CPU time 1.03 seconds
Started May 02 02:49:19 PM PDT 24
Finished May 02 02:49:22 PM PDT 24
Peak memory 215780 kb
Host smart-a7e46669-2504-4aa2-ada5-63d265f85635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733093546 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2733093546
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2510159013
Short name T919
Test name
Test status
Simulation time 12157573 ps
CPU time 0.94 seconds
Started May 02 02:49:11 PM PDT 24
Finished May 02 02:49:14 PM PDT 24
Peak memory 206260 kb
Host smart-94a4c429-47a3-47a1-82e7-be5bc1d42099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510159013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2510159013
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1714052354
Short name T884
Test name
Test status
Simulation time 45076028 ps
CPU time 0.87 seconds
Started May 02 02:49:12 PM PDT 24
Finished May 02 02:49:15 PM PDT 24
Peak memory 206188 kb
Host smart-03a3e1d2-8c1b-4553-9f14-25933ed54980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714052354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1714052354
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1209379788
Short name T880
Test name
Test status
Simulation time 351502830 ps
CPU time 1.25 seconds
Started May 02 02:49:17 PM PDT 24
Finished May 02 02:49:20 PM PDT 24
Peak memory 206320 kb
Host smart-21ca137a-232a-4ad1-8a9d-4015b182ef8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209379788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1209379788
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1084537817
Short name T962
Test name
Test status
Simulation time 81049763 ps
CPU time 2.48 seconds
Started May 02 02:49:11 PM PDT 24
Finished May 02 02:49:15 PM PDT 24
Peak memory 214572 kb
Host smart-e73ae6f1-b7ed-4fcc-946f-db68776dfbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084537817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1084537817
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2123375834
Short name T949
Test name
Test status
Simulation time 52163729 ps
CPU time 0.73 seconds
Started May 02 02:50:18 PM PDT 24
Finished May 02 02:50:20 PM PDT 24
Peak memory 205992 kb
Host smart-f25fd267-666f-4402-89d3-2237b2895cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123375834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2123375834
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3186443344
Short name T856
Test name
Test status
Simulation time 15860594 ps
CPU time 0.79 seconds
Started May 02 02:50:20 PM PDT 24
Finished May 02 02:50:22 PM PDT 24
Peak memory 206016 kb
Host smart-182d180c-4aff-4d9c-ae25-d2c57c88f943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186443344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3186443344
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3715253560
Short name T899
Test name
Test status
Simulation time 13350564 ps
CPU time 0.87 seconds
Started May 02 02:50:17 PM PDT 24
Finished May 02 02:50:19 PM PDT 24
Peak memory 206172 kb
Host smart-8325f4af-e6c5-409f-9d35-a7261f536aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715253560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3715253560
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.384464309
Short name T896
Test name
Test status
Simulation time 18913284 ps
CPU time 0.8 seconds
Started May 02 02:50:18 PM PDT 24
Finished May 02 02:50:21 PM PDT 24
Peak memory 205996 kb
Host smart-dd5624fe-b53c-4571-960f-6ac094ceb2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384464309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.384464309
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2767455222
Short name T841
Test name
Test status
Simulation time 78336584 ps
CPU time 0.8 seconds
Started May 02 02:50:18 PM PDT 24
Finished May 02 02:50:20 PM PDT 24
Peak memory 205980 kb
Host smart-ddf9d9a5-fe02-4213-92c1-23501caacf34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767455222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2767455222
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3662396899
Short name T869
Test name
Test status
Simulation time 18954316 ps
CPU time 0.96 seconds
Started May 02 02:50:17 PM PDT 24
Finished May 02 02:50:19 PM PDT 24
Peak memory 206128 kb
Host smart-9ae54df4-fcc1-4272-9aae-4bc0fe2f7105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662396899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3662396899
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2776043290
Short name T939
Test name
Test status
Simulation time 44931430 ps
CPU time 0.89 seconds
Started May 02 02:50:17 PM PDT 24
Finished May 02 02:50:19 PM PDT 24
Peak memory 206308 kb
Host smart-cb4c3e25-ca16-4f07-bc17-95905b76be74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776043290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2776043290
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3867303396
Short name T882
Test name
Test status
Simulation time 50804651 ps
CPU time 0.92 seconds
Started May 02 02:50:20 PM PDT 24
Finished May 02 02:50:22 PM PDT 24
Peak memory 206252 kb
Host smart-305b87fe-f6d2-4339-a89c-893a70ce77a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867303396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3867303396
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1365023204
Short name T913
Test name
Test status
Simulation time 25651182 ps
CPU time 0.92 seconds
Started May 02 02:50:21 PM PDT 24
Finished May 02 02:50:22 PM PDT 24
Peak memory 206240 kb
Host smart-f545c6e3-86aa-41eb-87d4-13a7e80bcb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365023204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1365023204
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3727959307
Short name T920
Test name
Test status
Simulation time 17512872 ps
CPU time 0.8 seconds
Started May 02 02:50:16 PM PDT 24
Finished May 02 02:50:18 PM PDT 24
Peak memory 206160 kb
Host smart-cfba2656-8b26-456b-9110-1c9154a72c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727959307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3727959307
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2627345427
Short name T904
Test name
Test status
Simulation time 26676628 ps
CPU time 1.74 seconds
Started May 02 02:49:27 PM PDT 24
Finished May 02 02:49:30 PM PDT 24
Peak memory 214604 kb
Host smart-1886bce8-0132-4ae7-bdc7-819463b6ba78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627345427 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2627345427
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.816257198
Short name T233
Test name
Test status
Simulation time 14596330 ps
CPU time 0.92 seconds
Started May 02 02:49:18 PM PDT 24
Finished May 02 02:49:21 PM PDT 24
Peak memory 206332 kb
Host smart-3047cb99-80ba-4ee4-88fc-145e21246c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816257198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.816257198
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2855897118
Short name T879
Test name
Test status
Simulation time 20306831 ps
CPU time 0.81 seconds
Started May 02 02:49:19 PM PDT 24
Finished May 02 02:49:21 PM PDT 24
Peak memory 206100 kb
Host smart-65b26dff-97b1-4322-b878-51a6d7e404f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855897118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2855897118
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1185685219
Short name T881
Test name
Test status
Simulation time 53024200 ps
CPU time 1.29 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206324 kb
Host smart-cea574c0-e5e0-4113-9eb5-19304299f8cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185685219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1185685219
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.740592762
Short name T917
Test name
Test status
Simulation time 141173833 ps
CPU time 2.48 seconds
Started May 02 02:49:17 PM PDT 24
Finished May 02 02:49:22 PM PDT 24
Peak memory 214544 kb
Host smart-e6071334-1e83-4182-b6f5-4ce23ae4b98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740592762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.740592762
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3931154098
Short name T944
Test name
Test status
Simulation time 333904334 ps
CPU time 2.52 seconds
Started May 02 02:49:18 PM PDT 24
Finished May 02 02:49:22 PM PDT 24
Peak memory 206700 kb
Host smart-c0e41284-4bca-4ae7-ab9a-aee054452630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931154098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3931154098
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2792693300
Short name T950
Test name
Test status
Simulation time 74064010 ps
CPU time 1.06 seconds
Started May 02 02:49:25 PM PDT 24
Finished May 02 02:49:27 PM PDT 24
Peak memory 214496 kb
Host smart-4b353911-bf7e-48af-8518-495acea08639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792693300 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2792693300
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2237982185
Short name T240
Test name
Test status
Simulation time 72419789 ps
CPU time 0.8 seconds
Started May 02 02:49:28 PM PDT 24
Finished May 02 02:49:30 PM PDT 24
Peak memory 206140 kb
Host smart-9baa07d7-4ae3-4d0f-8431-3f6a235a31a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237982185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2237982185
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3784650880
Short name T923
Test name
Test status
Simulation time 40584810 ps
CPU time 0.79 seconds
Started May 02 02:49:25 PM PDT 24
Finished May 02 02:49:27 PM PDT 24
Peak memory 206004 kb
Host smart-fb71de0a-61e2-4bca-ad18-6d23cd5559fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784650880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3784650880
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3180585950
Short name T891
Test name
Test status
Simulation time 75411682 ps
CPU time 1.11 seconds
Started May 02 02:49:25 PM PDT 24
Finished May 02 02:49:27 PM PDT 24
Peak memory 206320 kb
Host smart-2b0199fc-d93f-466b-8356-7307d37f7319
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180585950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3180585950
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1081484786
Short name T898
Test name
Test status
Simulation time 52792712 ps
CPU time 1.72 seconds
Started May 02 02:49:25 PM PDT 24
Finished May 02 02:49:27 PM PDT 24
Peak memory 214440 kb
Host smart-e9273b6b-b05f-4b32-a621-a5de2803e4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081484786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1081484786
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2618027026
Short name T935
Test name
Test status
Simulation time 622221025 ps
CPU time 2.51 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:34 PM PDT 24
Peak memory 206256 kb
Host smart-26fa3b89-5dcb-4927-9ddb-0d609be06a48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618027026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2618027026
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1687627030
Short name T872
Test name
Test status
Simulation time 25055936 ps
CPU time 1.57 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:34 PM PDT 24
Peak memory 214668 kb
Host smart-621b2b3f-d2b9-470e-9410-3e7f442451c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687627030 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1687627030
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1145861024
Short name T918
Test name
Test status
Simulation time 24652851 ps
CPU time 0.9 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206360 kb
Host smart-798e901d-47b0-4c3e-bce7-d1c467449e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145861024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1145861024
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1681096099
Short name T959
Test name
Test status
Simulation time 59033254 ps
CPU time 0.84 seconds
Started May 02 02:49:36 PM PDT 24
Finished May 02 02:49:38 PM PDT 24
Peak memory 206208 kb
Host smart-802bf34a-1509-4e44-a6df-a811706ab41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681096099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1681096099
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.4106974775
Short name T241
Test name
Test status
Simulation time 78295419 ps
CPU time 1.07 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206452 kb
Host smart-880f46d4-09a8-4364-8f27-a6b44b696681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106974775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.4106974775
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.4181931315
Short name T854
Test name
Test status
Simulation time 321215007 ps
CPU time 3.35 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:35 PM PDT 24
Peak memory 214620 kb
Host smart-732b2dcf-7e7d-4786-abcb-b02cc3820fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181931315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.4181931315
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2581563398
Short name T883
Test name
Test status
Simulation time 418012581 ps
CPU time 2.32 seconds
Started May 02 02:49:24 PM PDT 24
Finished May 02 02:49:28 PM PDT 24
Peak memory 206392 kb
Host smart-d5701f75-9cd0-433a-a8f4-11119ebe5958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581563398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2581563398
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1694638809
Short name T954
Test name
Test status
Simulation time 42393637 ps
CPU time 1.51 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:34 PM PDT 24
Peak memory 214664 kb
Host smart-2b30c4d0-8b1e-454c-9f09-7278ae4aebb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694638809 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1694638809
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4156623086
Short name T876
Test name
Test status
Simulation time 15521510 ps
CPU time 0.9 seconds
Started May 02 02:49:36 PM PDT 24
Finished May 02 02:49:38 PM PDT 24
Peak memory 206280 kb
Host smart-cf635417-4c84-411c-a5d9-a3074749184f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156623086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4156623086
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4115041487
Short name T888
Test name
Test status
Simulation time 21310914 ps
CPU time 0.89 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:34 PM PDT 24
Peak memory 206148 kb
Host smart-8af5da53-ff0d-4e04-b4d5-868ef384ee2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115041487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4115041487
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3317624112
Short name T889
Test name
Test status
Simulation time 33670601 ps
CPU time 1.08 seconds
Started May 02 02:49:32 PM PDT 24
Finished May 02 02:49:35 PM PDT 24
Peak memory 206276 kb
Host smart-633e550b-e093-4d7a-a957-452d5c075e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317624112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3317624112
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3749793231
Short name T875
Test name
Test status
Simulation time 96915649 ps
CPU time 2.01 seconds
Started May 02 02:49:32 PM PDT 24
Finished May 02 02:49:36 PM PDT 24
Peak memory 214628 kb
Host smart-c6debf75-3fe6-4c9d-9a63-e81a7725d5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749793231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3749793231
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3172994937
Short name T926
Test name
Test status
Simulation time 81701018 ps
CPU time 1.48 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206292 kb
Host smart-87927e6a-b91e-41b9-82fd-cbd6e1c97c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172994937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3172994937
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.630297562
Short name T851
Test name
Test status
Simulation time 56300936 ps
CPU time 1.73 seconds
Started May 02 02:49:29 PM PDT 24
Finished May 02 02:49:32 PM PDT 24
Peak memory 214632 kb
Host smart-902ffc59-18fe-4dd2-8a67-6a7404e2a89a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630297562 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.630297562
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2413358237
Short name T229
Test name
Test status
Simulation time 40206525 ps
CPU time 0.89 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206308 kb
Host smart-7a6a8c9d-797e-440d-9472-7db4f9c6e3b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413358237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2413358237
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4007963274
Short name T855
Test name
Test status
Simulation time 23785481 ps
CPU time 0.84 seconds
Started May 02 02:49:36 PM PDT 24
Finished May 02 02:49:38 PM PDT 24
Peak memory 206208 kb
Host smart-ddf8a766-a9ea-424c-b1f0-fe7e47e6d56a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007963274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4007963274
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4008655370
Short name T870
Test name
Test status
Simulation time 19214727 ps
CPU time 1.05 seconds
Started May 02 02:49:30 PM PDT 24
Finished May 02 02:49:33 PM PDT 24
Peak memory 206344 kb
Host smart-71c319d9-dabd-4569-8d43-2a9964851642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008655370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4008655370
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1174440666
Short name T907
Test name
Test status
Simulation time 112452788 ps
CPU time 2.64 seconds
Started May 02 02:49:31 PM PDT 24
Finished May 02 02:49:35 PM PDT 24
Peak memory 214552 kb
Host smart-d7d39ab9-7d2b-4882-a586-8cc91e9f389d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174440666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1174440666
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1668134955
Short name T951
Test name
Test status
Simulation time 179195870 ps
CPU time 1.55 seconds
Started May 02 02:49:36 PM PDT 24
Finished May 02 02:49:38 PM PDT 24
Peak memory 206348 kb
Host smart-f1d3388f-407c-4d25-8164-2de87b4dc991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668134955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1668134955
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.387328300
Short name T791
Test name
Test status
Simulation time 17637444 ps
CPU time 1 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 214728 kb
Host smart-22fa1ab7-e83b-49b2-9276-cb147c6b275e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387328300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.387328300
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2375408523
Short name T539
Test name
Test status
Simulation time 287248853 ps
CPU time 1.08 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 219328 kb
Host smart-c4a64b42-6f6b-47b2-a911-ae356bd10bb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375408523 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2375408523
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3225202600
Short name T314
Test name
Test status
Simulation time 20277245 ps
CPU time 1.15 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 232548 kb
Host smart-e0fb1d93-f0b0-4a2c-a161-defbe974094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225202600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3225202600
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2257509187
Short name T280
Test name
Test status
Simulation time 120032364 ps
CPU time 1.9 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:29 PM PDT 24
Peak memory 219824 kb
Host smart-613a7983-c277-4319-abba-e7f6eab7d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257509187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2257509187
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_smoke.3196028224
Short name T737
Test name
Test status
Simulation time 16442867 ps
CPU time 0.98 seconds
Started May 02 02:51:26 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 215168 kb
Host smart-7826ac3b-f020-42f1-b19d-a1cd03f0dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196028224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3196028224
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3893165937
Short name T633
Test name
Test status
Simulation time 257653365 ps
CPU time 4.01 seconds
Started May 02 02:51:27 PM PDT 24
Finished May 02 02:51:32 PM PDT 24
Peak memory 216832 kb
Host smart-a853ad96-b9e3-41bb-b342-fe0ff8ce35ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893165937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3893165937
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1944150560
Short name T693
Test name
Test status
Simulation time 557956004932 ps
CPU time 1110.39 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 03:09:55 PM PDT 24
Peak memory 223524 kb
Host smart-db48d8f2-55f6-43ff-8a32-e81254034747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944150560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1944150560
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1140674492
Short name T595
Test name
Test status
Simulation time 26710207 ps
CPU time 1.27 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 215560 kb
Host smart-96e74608-3f91-4692-80d6-41518718565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140674492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1140674492
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_err.2071138704
Short name T731
Test name
Test status
Simulation time 39394034 ps
CPU time 1.1 seconds
Started May 02 02:51:27 PM PDT 24
Finished May 02 02:51:29 PM PDT 24
Peak memory 219300 kb
Host smart-6ae097a7-83d0-42e5-a568-b04c590f1404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071138704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2071138704
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1836494873
Short name T290
Test name
Test status
Simulation time 45882854 ps
CPU time 1.62 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:28 PM PDT 24
Peak memory 217208 kb
Host smart-79723bfe-f151-46d2-9ff7-a8ffcc594b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836494873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1836494873
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1054587220
Short name T28
Test name
Test status
Simulation time 83642575 ps
CPU time 0.84 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:26 PM PDT 24
Peak memory 215364 kb
Host smart-4b86bd60-65ed-4658-a054-b37a36eadb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054587220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1054587220
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4139296447
Short name T16
Test name
Test status
Simulation time 993046729 ps
CPU time 10.01 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 236276 kb
Host smart-c06ed525-6b7a-4fe8-a795-dcae887b43ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139296447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4139296447
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3671892630
Short name T346
Test name
Test status
Simulation time 115999379 ps
CPU time 0.91 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:27 PM PDT 24
Peak memory 215172 kb
Host smart-722d71e8-08c5-4dda-97e7-8a1fd05891a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671892630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3671892630
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2809507473
Short name T218
Test name
Test status
Simulation time 355340333 ps
CPU time 6.92 seconds
Started May 02 02:51:25 PM PDT 24
Finished May 02 02:51:33 PM PDT 24
Peak memory 220136 kb
Host smart-5b78f063-1a36-47cf-9310-240acd1a0670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809507473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2809507473
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.611763074
Short name T206
Test name
Test status
Simulation time 64897082034 ps
CPU time 1388.33 seconds
Started May 02 02:51:28 PM PDT 24
Finished May 02 03:14:38 PM PDT 24
Peak memory 222224 kb
Host smart-e2b9bca1-896c-4de3-a8d1-2801320b3eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611763074 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.611763074
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.327517206
Short name T806
Test name
Test status
Simulation time 76864185 ps
CPU time 1.26 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 215524 kb
Host smart-80e8bc63-375a-4345-b5b4-9787f1df9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327517206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.327517206
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.216577430
Short name T372
Test name
Test status
Simulation time 57190314 ps
CPU time 0.97 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 214760 kb
Host smart-9fe51620-8144-4da0-add5-c128ebaddc71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216577430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.216577430
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1263216382
Short name T182
Test name
Test status
Simulation time 15415201 ps
CPU time 0.89 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 216092 kb
Host smart-987ffe1e-327e-492c-ac45-989d36862d12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263216382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1263216382
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1037681782
Short name T180
Test name
Test status
Simulation time 78476185 ps
CPU time 1.18 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 225428 kb
Host smart-4f0d8064-2d3d-4b38-b691-5254d4eed06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037681782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1037681782
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1379600408
Short name T618
Test name
Test status
Simulation time 47171941 ps
CPU time 1.27 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 218132 kb
Host smart-134dd160-9fdf-43b7-89ce-d971b6b0e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379600408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1379600408
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1635928044
Short name T475
Test name
Test status
Simulation time 35965564 ps
CPU time 1.31 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 216688 kb
Host smart-dcbdce20-90f5-4f98-89f9-cb91c4cad068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635928044 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1635928044
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3943788534
Short name T320
Test name
Test status
Simulation time 33361720 ps
CPU time 0.92 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 215172 kb
Host smart-6f469eb2-a4b2-42d8-ad5f-4d4214a18433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943788534 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3943788534
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.378656900
Short name T704
Test name
Test status
Simulation time 126697538 ps
CPU time 2.95 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 216764 kb
Host smart-73310e78-cfa9-4a9a-ad82-d2a3de818b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378656900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.378656900
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1204222503
Short name T642
Test name
Test status
Simulation time 29973499622 ps
CPU time 332.52 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:57:29 PM PDT 24
Peak memory 220164 kb
Host smart-462b9a70-17d4-4d78-9a56-a9dededbc3f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204222503 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1204222503
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1898419876
Short name T329
Test name
Test status
Simulation time 776915617 ps
CPU time 5.4 seconds
Started May 02 02:53:49 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 219612 kb
Host smart-9bd8b778-2c81-4465-8385-75965c87f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898419876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1898419876
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3458922503
Short name T477
Test name
Test status
Simulation time 62282860 ps
CPU time 1.24 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 216816 kb
Host smart-ae16af46-be95-4217-b3dc-1c4d34f42ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458922503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3458922503
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1124785938
Short name T94
Test name
Test status
Simulation time 40468257 ps
CPU time 1.52 seconds
Started May 02 02:53:44 PM PDT 24
Finished May 02 02:53:47 PM PDT 24
Peak memory 216876 kb
Host smart-3cfc1c31-3f31-4eab-be5e-3675ed5e3457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124785938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1124785938
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.335408686
Short name T20
Test name
Test status
Simulation time 33534672 ps
CPU time 1.36 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 218272 kb
Host smart-92bfc328-c90b-4ca5-875c-deee6d50de28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335408686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.335408686
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2243415814
Short name T493
Test name
Test status
Simulation time 49737397 ps
CPU time 1.66 seconds
Started May 02 02:53:54 PM PDT 24
Finished May 02 02:53:59 PM PDT 24
Peak memory 219412 kb
Host smart-44e1d51f-6c4a-4537-8b7e-c64007727d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243415814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2243415814
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.973454787
Short name T616
Test name
Test status
Simulation time 35708537 ps
CPU time 1.38 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:57 PM PDT 24
Peak memory 218252 kb
Host smart-2a946d2c-22e0-4099-82cc-9d0a328cf329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973454787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.973454787
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3844139803
Short name T366
Test name
Test status
Simulation time 230775111 ps
CPU time 1.94 seconds
Started May 02 02:53:49 PM PDT 24
Finished May 02 02:53:53 PM PDT 24
Peak memory 218324 kb
Host smart-b00fd460-4b6e-4bd1-b89e-0f56c6a9557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844139803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3844139803
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2921514783
Short name T782
Test name
Test status
Simulation time 182106559 ps
CPU time 1.24 seconds
Started May 02 02:51:55 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 215596 kb
Host smart-2bcda8fe-e1ba-4485-9fe0-6b1a1fb61bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921514783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2921514783
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2214084792
Short name T165
Test name
Test status
Simulation time 41853629 ps
CPU time 0.79 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:55 PM PDT 24
Peak memory 205896 kb
Host smart-1eadd977-d461-481e-82ef-138d646cf299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214084792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2214084792
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1422212548
Short name T789
Test name
Test status
Simulation time 21121341 ps
CPU time 0.88 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 216032 kb
Host smart-400c9840-a166-4614-b1a5-9a036f5d964e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422212548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1422212548
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2793234333
Short name T97
Test name
Test status
Simulation time 30547933 ps
CPU time 1.28 seconds
Started May 02 02:51:55 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 229676 kb
Host smart-70ce9798-3903-4c32-a677-687be3dd386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793234333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2793234333
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1878166035
Short name T604
Test name
Test status
Simulation time 88814338 ps
CPU time 1.18 seconds
Started May 02 02:51:55 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 216772 kb
Host smart-e2adabfa-146c-4d83-8484-4c466392f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878166035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1878166035
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3933191058
Short name T323
Test name
Test status
Simulation time 23315743 ps
CPU time 1.12 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 215440 kb
Host smart-e5454e34-f22c-477a-9613-b1ba4fee4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933191058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3933191058
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.660196881
Short name T755
Test name
Test status
Simulation time 16865813 ps
CPU time 1.01 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 215204 kb
Host smart-e09ea261-3365-46c8-9873-b63e3afd3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660196881 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.660196881
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4080822027
Short name T158
Test name
Test status
Simulation time 548695507 ps
CPU time 3.39 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 216816 kb
Host smart-5463a3b3-59b1-4516-93ac-0a4d5235ebc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080822027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4080822027
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1519504088
Short name T760
Test name
Test status
Simulation time 59141560876 ps
CPU time 952.39 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 03:07:50 PM PDT 24
Peak memory 219648 kb
Host smart-2285593f-1359-49c8-b492-adb90653d95d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519504088 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1519504088
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3862911146
Short name T569
Test name
Test status
Simulation time 30451995 ps
CPU time 1.43 seconds
Started May 02 02:53:50 PM PDT 24
Finished May 02 02:53:54 PM PDT 24
Peak memory 218208 kb
Host smart-6eb83456-e3ae-4a3b-8e57-e9a08f332b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862911146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3862911146
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2788988343
Short name T517
Test name
Test status
Simulation time 37196136 ps
CPU time 1.2 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 217036 kb
Host smart-7321b61c-0ea5-4ab0-855c-bc85785ba19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788988343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2788988343
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1780249853
Short name T547
Test name
Test status
Simulation time 24770206 ps
CPU time 1.28 seconds
Started May 02 02:53:50 PM PDT 24
Finished May 02 02:53:54 PM PDT 24
Peak memory 219536 kb
Host smart-65d9156e-8017-4560-9d5e-205334968c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780249853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1780249853
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.486787684
Short name T575
Test name
Test status
Simulation time 37958824 ps
CPU time 1.38 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:55 PM PDT 24
Peak memory 217072 kb
Host smart-25355003-5f80-4a54-b8ed-c01472ac2c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486787684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.486787684
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1376402824
Short name T279
Test name
Test status
Simulation time 38925308 ps
CPU time 1.45 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 218188 kb
Host smart-18c3aedc-237d-4ec2-b143-b46e9e8499cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376402824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1376402824
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3675443375
Short name T11
Test name
Test status
Simulation time 41759479 ps
CPU time 1.61 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:59 PM PDT 24
Peak memory 219544 kb
Host smart-2998338d-0d5b-4d28-b870-4ec11b55ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675443375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3675443375
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.243716818
Short name T373
Test name
Test status
Simulation time 68165890 ps
CPU time 1.09 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 216872 kb
Host smart-41a9cab9-affc-422c-87fe-582a3950e598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243716818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.243716818
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3599550871
Short name T713
Test name
Test status
Simulation time 36743647 ps
CPU time 1.36 seconds
Started May 02 02:53:57 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 219484 kb
Host smart-7c641ceb-9711-4f2e-bdcb-953cdd836825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599550871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3599550871
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.743214473
Short name T754
Test name
Test status
Simulation time 40361996 ps
CPU time 0.86 seconds
Started May 02 02:51:55 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 214748 kb
Host smart-4898da55-4f82-42b2-a899-4ecddff2ec08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743214473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.743214473
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2325202890
Short name T174
Test name
Test status
Simulation time 12800530 ps
CPU time 0.86 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 216192 kb
Host smart-b400131f-fb6b-438e-81cf-a349b0f8f9a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325202890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2325202890
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4002607729
Short name T800
Test name
Test status
Simulation time 78906905 ps
CPU time 1.18 seconds
Started May 02 02:51:55 PM PDT 24
Finished May 02 02:51:58 PM PDT 24
Peak memory 216604 kb
Host smart-6ba8775c-2c8c-468c-b246-400f38482541
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002607729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4002607729
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3108591145
Short name T188
Test name
Test status
Simulation time 41821864 ps
CPU time 1.19 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:55 PM PDT 24
Peak memory 225360 kb
Host smart-9a222ea7-b2c6-4318-90f4-1db98daf0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108591145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3108591145
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.660507372
Short name T425
Test name
Test status
Simulation time 189564836 ps
CPU time 1.23 seconds
Started May 02 02:51:56 PM PDT 24
Finished May 02 02:51:59 PM PDT 24
Peak memory 218460 kb
Host smart-dd9c7ea0-029f-4a7a-82b4-d58b0d195d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660507372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.660507372
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3534446186
Short name T709
Test name
Test status
Simulation time 24054427 ps
CPU time 1.17 seconds
Started May 02 02:51:57 PM PDT 24
Finished May 02 02:52:00 PM PDT 24
Peak memory 223872 kb
Host smart-47bba274-c522-42c5-aabf-182a003a7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534446186 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3534446186
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2832825998
Short name T757
Test name
Test status
Simulation time 23852847 ps
CPU time 0.88 seconds
Started May 02 02:51:53 PM PDT 24
Finished May 02 02:51:56 PM PDT 24
Peak memory 215136 kb
Host smart-38895145-161a-4928-9842-94996f8ff675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832825998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2832825998
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.970878760
Short name T540
Test name
Test status
Simulation time 225051764779 ps
CPU time 983.1 seconds
Started May 02 02:51:53 PM PDT 24
Finished May 02 03:08:18 PM PDT 24
Peak memory 223212 kb
Host smart-6dc47b42-00ba-457c-90b0-b1617bf843f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970878760 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.970878760
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1832623622
Short name T750
Test name
Test status
Simulation time 29053235 ps
CPU time 1.28 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 218152 kb
Host smart-022487bf-493a-4742-8cbe-e4555af6b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832623622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1832623622
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.853047513
Short name T414
Test name
Test status
Simulation time 49535515 ps
CPU time 1.1 seconds
Started May 02 02:53:50 PM PDT 24
Finished May 02 02:53:54 PM PDT 24
Peak memory 216696 kb
Host smart-5109154a-e93e-40e0-a484-d273e2445785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853047513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.853047513
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.485437203
Short name T671
Test name
Test status
Simulation time 47768624 ps
CPU time 1.08 seconds
Started May 02 02:53:54 PM PDT 24
Finished May 02 02:53:59 PM PDT 24
Peak memory 216808 kb
Host smart-3e3e250b-04df-45da-a32a-852ad540a5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485437203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.485437203
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3840762971
Short name T375
Test name
Test status
Simulation time 51195199 ps
CPU time 1.25 seconds
Started May 02 02:53:54 PM PDT 24
Finished May 02 02:53:59 PM PDT 24
Peak memory 218000 kb
Host smart-99229cd1-dd61-4858-bdbb-42c176d19d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840762971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3840762971
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1015764177
Short name T513
Test name
Test status
Simulation time 111014243 ps
CPU time 1.48 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 218628 kb
Host smart-4af85fe6-cad7-4d7d-916e-a3fcfc5b3089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015764177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1015764177
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2771850996
Short name T739
Test name
Test status
Simulation time 89693909 ps
CPU time 1.34 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 218452 kb
Host smart-fc9c4f30-2e87-4441-8391-857c0c486661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771850996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2771850996
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3783550093
Short name T44
Test name
Test status
Simulation time 27061196 ps
CPU time 1.19 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:58 PM PDT 24
Peak memory 216720 kb
Host smart-509296db-4e2a-4a97-b8d3-a27576a5d3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783550093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3783550093
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3145261552
Short name T291
Test name
Test status
Simulation time 22363331 ps
CPU time 1.17 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:57 PM PDT 24
Peak memory 217144 kb
Host smart-932d6c38-24b9-4709-bc1c-d506f346f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145261552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3145261552
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1257943135
Short name T76
Test name
Test status
Simulation time 294186899 ps
CPU time 3.43 seconds
Started May 02 02:53:54 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 219820 kb
Host smart-606f98be-077f-49a6-aa42-3acfad1aa000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257943135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1257943135
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1047052013
Short name T326
Test name
Test status
Simulation time 22627096 ps
CPU time 1.1 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 217020 kb
Host smart-cfad4c16-a827-4849-9c30-59fd114bec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047052013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1047052013
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2341366758
Short name T327
Test name
Test status
Simulation time 29969599 ps
CPU time 0.92 seconds
Started May 02 02:52:00 PM PDT 24
Finished May 02 02:52:02 PM PDT 24
Peak memory 206484 kb
Host smart-806cbc99-98ac-4b70-910e-d48d9670ff23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341366758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2341366758
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4252210121
Short name T745
Test name
Test status
Simulation time 25886683 ps
CPU time 1.08 seconds
Started May 02 02:52:02 PM PDT 24
Finished May 02 02:52:04 PM PDT 24
Peak memory 216608 kb
Host smart-b4b86f08-fa15-4d76-a7b1-cbb992f60c4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252210121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4252210121
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.398396601
Short name T166
Test name
Test status
Simulation time 21958486 ps
CPU time 0.95 seconds
Started May 02 02:52:01 PM PDT 24
Finished May 02 02:52:03 PM PDT 24
Peak memory 218372 kb
Host smart-7e3e7ea2-217b-4023-893b-0748aa87e23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398396601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.398396601
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1969020522
Short name T348
Test name
Test status
Simulation time 33800231 ps
CPU time 1.02 seconds
Started May 02 02:52:03 PM PDT 24
Finished May 02 02:52:05 PM PDT 24
Peak memory 216824 kb
Host smart-3b67241b-62ce-4c68-9e60-dffc0fdd1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969020522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1969020522
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2499301214
Short name T345
Test name
Test status
Simulation time 31088134 ps
CPU time 1.33 seconds
Started May 02 02:51:59 PM PDT 24
Finished May 02 02:52:01 PM PDT 24
Peak memory 224648 kb
Host smart-92211646-dd74-4307-a94b-8d4ce3dff95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499301214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2499301214
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1572777059
Short name T394
Test name
Test status
Simulation time 20673348 ps
CPU time 0.92 seconds
Started May 02 02:51:54 PM PDT 24
Finished May 02 02:51:57 PM PDT 24
Peak memory 215164 kb
Host smart-be3ef711-14d0-48ae-9995-cd93ea71de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572777059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1572777059
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3820565265
Short name T48
Test name
Test status
Simulation time 492263844 ps
CPU time 3.03 seconds
Started May 02 02:52:05 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 216772 kb
Host smart-f8ee11b8-0415-4e88-8498-a5bc62dce83f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820565265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3820565265
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1828016073
Short name T819
Test name
Test status
Simulation time 399446320899 ps
CPU time 2193.02 seconds
Started May 02 02:52:03 PM PDT 24
Finished May 02 03:28:38 PM PDT 24
Peak memory 229484 kb
Host smart-0ba027e9-70b2-45ce-b453-887897a0116c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828016073 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1828016073
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2061634722
Short name T732
Test name
Test status
Simulation time 71583078 ps
CPU time 1.69 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:59 PM PDT 24
Peak memory 218456 kb
Host smart-7af91048-a33c-4e29-a730-19afbb487621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061634722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2061634722
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3393173791
Short name T715
Test name
Test status
Simulation time 55285921 ps
CPU time 1.7 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:55 PM PDT 24
Peak memory 218264 kb
Host smart-bf2e1fc5-10f4-457d-a4e0-d4e7b31bb234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393173791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3393173791
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1141706500
Short name T675
Test name
Test status
Simulation time 86025805 ps
CPU time 2.97 seconds
Started May 02 02:53:54 PM PDT 24
Finished May 02 02:54:01 PM PDT 24
Peak memory 219648 kb
Host smart-47f00e57-ae09-4528-a35b-ca40361ab87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141706500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1141706500
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.219194504
Short name T86
Test name
Test status
Simulation time 121237184 ps
CPU time 1.81 seconds
Started May 02 02:53:52 PM PDT 24
Finished May 02 02:53:57 PM PDT 24
Peak memory 218208 kb
Host smart-e11ef7bf-abe5-49d3-a2a2-2528c940392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219194504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.219194504
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3075911868
Short name T285
Test name
Test status
Simulation time 82469336 ps
CPU time 1.84 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:56 PM PDT 24
Peak memory 218112 kb
Host smart-94e3f9c1-cbed-4169-a499-f53a02bb88df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075911868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3075911868
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3619428866
Short name T201
Test name
Test status
Simulation time 49416641 ps
CPU time 1.81 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:58 PM PDT 24
Peak memory 216900 kb
Host smart-481e4b10-8af6-4851-a734-b5e17847bae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619428866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3619428866
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1426117519
Short name T531
Test name
Test status
Simulation time 101698312 ps
CPU time 1.35 seconds
Started May 02 02:53:53 PM PDT 24
Finished May 02 02:53:57 PM PDT 24
Peak memory 219376 kb
Host smart-be84c95f-96d2-4136-9841-74f82a86c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426117519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1426117519
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.694893985
Short name T213
Test name
Test status
Simulation time 78166014 ps
CPU time 1.65 seconds
Started May 02 02:53:50 PM PDT 24
Finished May 02 02:53:55 PM PDT 24
Peak memory 218500 kb
Host smart-3af1d477-9927-455f-821f-82d14dd5bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694893985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.694893985
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3999614901
Short name T46
Test name
Test status
Simulation time 53887071 ps
CPU time 1.61 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:52 PM PDT 24
Peak memory 218040 kb
Host smart-877bcb50-9255-4683-abfe-cd56d2c931cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999614901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3999614901
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.237648921
Short name T248
Test name
Test status
Simulation time 21976975 ps
CPU time 1.25 seconds
Started May 02 02:52:02 PM PDT 24
Finished May 02 02:52:04 PM PDT 24
Peak memory 215536 kb
Host smart-ade63b2b-db47-4f1b-b7eb-2dede9ac6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237648921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.237648921
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1054431348
Short name T66
Test name
Test status
Simulation time 47196083 ps
CPU time 0.9 seconds
Started May 02 02:52:03 PM PDT 24
Finished May 02 02:52:05 PM PDT 24
Peak memory 214704 kb
Host smart-c5eb6535-a88a-41fc-a218-2969ad1e29cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054431348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1054431348
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.161013945
Short name T194
Test name
Test status
Simulation time 11622829 ps
CPU time 0.88 seconds
Started May 02 02:52:04 PM PDT 24
Finished May 02 02:52:06 PM PDT 24
Peak memory 216208 kb
Host smart-05255a8e-0c28-4095-80fa-19ab38273fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161013945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.161013945
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3316531884
Short name T69
Test name
Test status
Simulation time 69716887 ps
CPU time 1.14 seconds
Started May 02 02:51:59 PM PDT 24
Finished May 02 02:52:01 PM PDT 24
Peak memory 217980 kb
Host smart-afb369e6-6db0-4536-b9dd-bcee115edf2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316531884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3316531884
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1401751842
Short name T367
Test name
Test status
Simulation time 23133018 ps
CPU time 0.94 seconds
Started May 02 02:52:05 PM PDT 24
Finished May 02 02:52:07 PM PDT 24
Peak memory 217948 kb
Host smart-3a78fcb9-881f-4afc-8b7b-a0a263f1f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401751842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1401751842
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.295858340
Short name T340
Test name
Test status
Simulation time 61944599 ps
CPU time 1.23 seconds
Started May 02 02:52:01 PM PDT 24
Finished May 02 02:52:03 PM PDT 24
Peak memory 216712 kb
Host smart-b18edfa0-c61c-4b11-aff1-2b1df4469005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295858340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.295858340
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2207953302
Short name T532
Test name
Test status
Simulation time 23008987 ps
CPU time 1.1 seconds
Started May 02 02:52:03 PM PDT 24
Finished May 02 02:52:06 PM PDT 24
Peak memory 223896 kb
Host smart-637ef6b6-5b68-4a83-acdc-1a0b784c8087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207953302 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2207953302
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.298134297
Short name T304
Test name
Test status
Simulation time 43961420 ps
CPU time 0.95 seconds
Started May 02 02:52:02 PM PDT 24
Finished May 02 02:52:04 PM PDT 24
Peak memory 215180 kb
Host smart-a285831b-a118-4ac6-84c9-226f5f032d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298134297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.298134297
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3959133423
Short name T620
Test name
Test status
Simulation time 499492140 ps
CPU time 2.16 seconds
Started May 02 02:52:00 PM PDT 24
Finished May 02 02:52:03 PM PDT 24
Peak memory 215140 kb
Host smart-5030b0db-8836-46a1-aee9-a0ce0db719bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959133423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3959133423
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1482385960
Short name T689
Test name
Test status
Simulation time 62082547340 ps
CPU time 1445.82 seconds
Started May 02 02:52:04 PM PDT 24
Finished May 02 03:16:11 PM PDT 24
Peak memory 222236 kb
Host smart-86c43da6-b154-4766-b497-c6e32ad6f9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482385960 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1482385960
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.862172649
Short name T512
Test name
Test status
Simulation time 174806255 ps
CPU time 1.12 seconds
Started May 02 02:53:57 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 216896 kb
Host smart-700b34f4-0f64-4dc2-8372-6cfa16c46a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862172649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.862172649
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3224429831
Short name T515
Test name
Test status
Simulation time 83289178 ps
CPU time 1.54 seconds
Started May 02 02:53:57 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 219276 kb
Host smart-1fe6d023-d6f6-49c2-9795-62ecd3e394ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224429831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3224429831
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1595889660
Short name T482
Test name
Test status
Simulation time 78063074 ps
CPU time 1.38 seconds
Started May 02 02:53:57 PM PDT 24
Finished May 02 02:54:01 PM PDT 24
Peak memory 218144 kb
Host smart-83d3d9e5-f2d1-4be1-a832-871fee65ec5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595889660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1595889660
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3055582523
Short name T388
Test name
Test status
Simulation time 43719379 ps
CPU time 1.24 seconds
Started May 02 02:53:58 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 216828 kb
Host smart-8722deed-b3bb-444e-b166-f3a5ee4a4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055582523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3055582523
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1392586363
Short name T762
Test name
Test status
Simulation time 70633016 ps
CPU time 2.38 seconds
Started May 02 02:53:58 PM PDT 24
Finished May 02 02:54:04 PM PDT 24
Peak memory 218196 kb
Host smart-dd404b30-0062-490b-8f58-b3c7cfa5575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392586363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1392586363
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1844555410
Short name T613
Test name
Test status
Simulation time 51335632 ps
CPU time 1.07 seconds
Started May 02 02:53:57 PM PDT 24
Finished May 02 02:54:01 PM PDT 24
Peak memory 216872 kb
Host smart-ad4134d1-5b98-427f-81ff-fccd28621989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844555410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1844555410
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.519978618
Short name T747
Test name
Test status
Simulation time 126092734 ps
CPU time 2.4 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:08 PM PDT 24
Peak memory 219168 kb
Host smart-b6f68538-9e31-4899-a816-a5f734feda00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519978618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.519978618
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3069317674
Short name T681
Test name
Test status
Simulation time 41314244 ps
CPU time 1.24 seconds
Started May 02 02:53:58 PM PDT 24
Finished May 02 02:54:03 PM PDT 24
Peak memory 216704 kb
Host smart-f212c807-8256-4cfd-a94a-749b9a8d924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069317674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3069317674
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1466416477
Short name T159
Test name
Test status
Simulation time 85595567 ps
CPU time 1.03 seconds
Started May 02 02:53:59 PM PDT 24
Finished May 02 02:54:03 PM PDT 24
Peak memory 216932 kb
Host smart-2c47fce6-ac6a-43a6-b6d5-053a62cb0868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466416477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1466416477
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1473881780
Short name T499
Test name
Test status
Simulation time 51344452 ps
CPU time 1.45 seconds
Started May 02 02:54:00 PM PDT 24
Finished May 02 02:54:04 PM PDT 24
Peak memory 216972 kb
Host smart-1e3f746a-bcfe-4253-8257-0d0f6e83d1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473881780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1473881780
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2290534865
Short name T89
Test name
Test status
Simulation time 46723441 ps
CPU time 1.21 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:08 PM PDT 24
Peak memory 215552 kb
Host smart-26746faa-30f3-4946-ae35-b466c5511fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290534865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2290534865
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.979847978
Short name T332
Test name
Test status
Simulation time 23778032 ps
CPU time 0.82 seconds
Started May 02 02:52:10 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 206740 kb
Host smart-1ef46ecd-f42e-49ba-b7fd-e8181493d85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979847978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.979847978
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1826014986
Short name T192
Test name
Test status
Simulation time 11968353 ps
CPU time 0.87 seconds
Started May 02 02:52:07 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 215416 kb
Host smart-8fcc4733-d486-4aa2-98d6-76a1881c7306
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826014986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1826014986
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1587454160
Short name T609
Test name
Test status
Simulation time 29447063 ps
CPU time 1.05 seconds
Started May 02 02:52:07 PM PDT 24
Finished May 02 02:52:10 PM PDT 24
Peak memory 217896 kb
Host smart-591a0df6-4bb3-43a8-83a4-936fdd252b8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587454160 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1587454160
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.657584362
Short name T580
Test name
Test status
Simulation time 29789059 ps
CPU time 0.91 seconds
Started May 02 02:52:08 PM PDT 24
Finished May 02 02:52:11 PM PDT 24
Peak memory 218292 kb
Host smart-45f318bc-a1ba-4527-b968-bfeb978c9068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657584362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.657584362
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.391173129
Short name T444
Test name
Test status
Simulation time 78227060 ps
CPU time 1.03 seconds
Started May 02 02:52:01 PM PDT 24
Finished May 02 02:52:03 PM PDT 24
Peak memory 216944 kb
Host smart-a600a53f-cae8-45c8-af97-c38bfd7fd4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391173129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.391173129
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3281427791
Short name T416
Test name
Test status
Simulation time 26379275 ps
CPU time 0.91 seconds
Started May 02 02:52:00 PM PDT 24
Finished May 02 02:52:02 PM PDT 24
Peak memory 215112 kb
Host smart-c2f680b3-fbcf-4c63-b522-378cb585da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281427791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3281427791
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3752799864
Short name T217
Test name
Test status
Simulation time 288447039 ps
CPU time 5.45 seconds
Started May 02 02:52:08 PM PDT 24
Finished May 02 02:52:15 PM PDT 24
Peak memory 218236 kb
Host smart-f1b1440d-bb6d-4045-920d-4ad8e4786d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752799864 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3752799864
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1687733866
Short name T210
Test name
Test status
Simulation time 257654083383 ps
CPU time 1425.3 seconds
Started May 02 02:52:05 PM PDT 24
Finished May 02 03:15:52 PM PDT 24
Peak memory 223912 kb
Host smart-4f49d150-c826-4581-8f6c-4b1fac5d2e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687733866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1687733866
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3432479403
Short name T535
Test name
Test status
Simulation time 53315503 ps
CPU time 1.49 seconds
Started May 02 02:53:56 PM PDT 24
Finished May 02 02:54:01 PM PDT 24
Peak memory 218180 kb
Host smart-468eaea1-1082-4f33-aeee-0d78632882fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432479403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3432479403
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.4288458481
Short name T378
Test name
Test status
Simulation time 95431802 ps
CPU time 1.17 seconds
Started May 02 02:53:58 PM PDT 24
Finished May 02 02:54:02 PM PDT 24
Peak memory 216760 kb
Host smart-f0e9ab24-a9e9-4b67-8406-365b35c68dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288458481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.4288458481
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4018135250
Short name T507
Test name
Test status
Simulation time 48180164 ps
CPU time 1.52 seconds
Started May 02 02:53:55 PM PDT 24
Finished May 02 02:54:01 PM PDT 24
Peak memory 217996 kb
Host smart-b3d9b3c8-992e-4aea-8973-ca63b15535ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018135250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4018135250
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3762557442
Short name T84
Test name
Test status
Simulation time 91386057 ps
CPU time 1.56 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 218204 kb
Host smart-30675652-0919-4b90-acaf-92d124afc350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762557442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3762557442
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.540516916
Short name T489
Test name
Test status
Simulation time 25369783 ps
CPU time 1.24 seconds
Started May 02 02:54:09 PM PDT 24
Finished May 02 02:54:12 PM PDT 24
Peak memory 218216 kb
Host smart-8ddacfb2-07e8-4b10-8d60-59f9a31b5747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540516916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.540516916
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4266882221
Short name T393
Test name
Test status
Simulation time 138523190 ps
CPU time 1.5 seconds
Started May 02 02:54:05 PM PDT 24
Finished May 02 02:54:08 PM PDT 24
Peak memory 215204 kb
Host smart-296a7f20-6fb3-4c0c-b55d-c9142481c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266882221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4266882221
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3205060665
Short name T525
Test name
Test status
Simulation time 126638157 ps
CPU time 1.17 seconds
Started May 02 02:54:09 PM PDT 24
Finished May 02 02:54:11 PM PDT 24
Peak memory 216908 kb
Host smart-58b7f1e2-d693-4747-817a-f4209ac7c8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205060665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3205060665
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1112156676
Short name T502
Test name
Test status
Simulation time 474587540 ps
CPU time 4.65 seconds
Started May 02 02:54:01 PM PDT 24
Finished May 02 02:54:08 PM PDT 24
Peak memory 219092 kb
Host smart-6709fbe4-cfde-42cb-a720-2ccb58697ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112156676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1112156676
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.902844943
Short name T726
Test name
Test status
Simulation time 218756330 ps
CPU time 1.47 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 216820 kb
Host smart-e7eb55d1-6cff-45c1-84b1-72427a023070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902844943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.902844943
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3271656355
Short name T149
Test name
Test status
Simulation time 27404204 ps
CPU time 1.28 seconds
Started May 02 02:52:10 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 215580 kb
Host smart-3784f489-4305-4aff-8fea-a01af3839820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271656355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3271656355
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.823676769
Short name T357
Test name
Test status
Simulation time 50893323 ps
CPU time 0.9 seconds
Started May 02 02:52:10 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 206520 kb
Host smart-50cadc06-f867-46ac-99ff-400918fbd142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823676769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.823676769
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3977035656
Short name T186
Test name
Test status
Simulation time 12337574 ps
CPU time 0.94 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 216236 kb
Host smart-a5ae01e5-cd53-478a-b32e-1332d7771385
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977035656 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3977035656
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_genbits.3763440846
Short name T376
Test name
Test status
Simulation time 43415580 ps
CPU time 1.52 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 218124 kb
Host smart-dc320202-bb29-4631-90b5-cda300e00c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763440846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3763440846
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2871264403
Short name T431
Test name
Test status
Simulation time 44342184 ps
CPU time 0.79 seconds
Started May 02 02:52:07 PM PDT 24
Finished May 02 02:52:10 PM PDT 24
Peak memory 215208 kb
Host smart-6baf453f-5cda-45c9-a1b7-ed9f2f9386a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871264403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2871264403
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3798865245
Short name T522
Test name
Test status
Simulation time 24041063 ps
CPU time 0.94 seconds
Started May 02 02:52:10 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 206944 kb
Host smart-03375ebf-f22f-4b97-a875-1f243d0f9251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798865245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3798865245
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.385217632
Short name T530
Test name
Test status
Simulation time 154181542 ps
CPU time 2.2 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:10 PM PDT 24
Peak memory 216872 kb
Host smart-c6e1cd7d-df45-4b5c-8ddb-60be16f8927d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385217632 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.385217632
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3951567890
Short name T200
Test name
Test status
Simulation time 24284427113 ps
CPU time 410.98 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:58:58 PM PDT 24
Peak memory 218084 kb
Host smart-50b9b7a7-94b1-45de-85a4-be8c7d51948f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951567890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3951567890
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3978943400
Short name T306
Test name
Test status
Simulation time 34906820 ps
CPU time 1.46 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 218276 kb
Host smart-1633126d-9b57-47c9-9bd8-225cf7a2b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978943400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3978943400
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2812776140
Short name T402
Test name
Test status
Simulation time 47735768 ps
CPU time 1.25 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 218332 kb
Host smart-d513a412-4899-4d70-90b0-36b0e44d4339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812776140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2812776140
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1363521973
Short name T733
Test name
Test status
Simulation time 48442062 ps
CPU time 1.58 seconds
Started May 02 02:54:06 PM PDT 24
Finished May 02 02:54:09 PM PDT 24
Peak memory 218008 kb
Host smart-f52d2b50-b61f-4959-a23f-90ad67b534e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363521973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1363521973
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.367391888
Short name T483
Test name
Test status
Simulation time 41483567 ps
CPU time 1.38 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 218324 kb
Host smart-ec651b9f-5982-47a2-8140-a8a1df8cea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367391888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.367391888
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.165700761
Short name T309
Test name
Test status
Simulation time 39236819 ps
CPU time 1.57 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:06 PM PDT 24
Peak memory 218132 kb
Host smart-00b47cc1-3ead-4065-b891-e59fe40563a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165700761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.165700761
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3221842515
Short name T302
Test name
Test status
Simulation time 145277164 ps
CPU time 1.09 seconds
Started May 02 02:54:06 PM PDT 24
Finished May 02 02:54:09 PM PDT 24
Peak memory 216908 kb
Host smart-be7653a0-810f-4af9-8817-adfd01230dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221842515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3221842515
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.91327304
Short name T322
Test name
Test status
Simulation time 66424821 ps
CPU time 1.1 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:06 PM PDT 24
Peak memory 217008 kb
Host smart-49d350d6-c9f9-4f80-aab9-8ccd414cf8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91327304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.91327304
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2910851641
Short name T286
Test name
Test status
Simulation time 45965371 ps
CPU time 1.5 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 219368 kb
Host smart-49d80b14-3b64-49df-93b0-5e33a07f1cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910851641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2910851641
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3020113286
Short name T57
Test name
Test status
Simulation time 40900974 ps
CPU time 1.17 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 216768 kb
Host smart-21bd4676-97b6-4fd1-8db5-5d6325c918a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020113286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3020113286
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2710602035
Short name T602
Test name
Test status
Simulation time 147595581 ps
CPU time 1.04 seconds
Started May 02 02:54:06 PM PDT 24
Finished May 02 02:54:09 PM PDT 24
Peak memory 216864 kb
Host smart-004309a1-ce33-4e76-89ed-33e45e56211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710602035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2710602035
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2531323274
Short name T823
Test name
Test status
Simulation time 54590953 ps
CPU time 1.21 seconds
Started May 02 02:52:07 PM PDT 24
Finished May 02 02:52:10 PM PDT 24
Peak memory 215452 kb
Host smart-c6b89f19-a704-4c80-8e64-c1c440216ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531323274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2531323274
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2187025724
Short name T719
Test name
Test status
Simulation time 21223537 ps
CPU time 0.93 seconds
Started May 02 02:52:17 PM PDT 24
Finished May 02 02:52:19 PM PDT 24
Peak memory 214736 kb
Host smart-82179f1a-979f-4e67-82f0-e6dd0517aa5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187025724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2187025724
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1346653044
Short name T138
Test name
Test status
Simulation time 32327293 ps
CPU time 0.84 seconds
Started May 02 02:52:08 PM PDT 24
Finished May 02 02:52:10 PM PDT 24
Peak memory 215988 kb
Host smart-6960bb43-7043-4520-b871-6d5f5d885a94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346653044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1346653044
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1542955682
Short name T438
Test name
Test status
Simulation time 56774167 ps
CPU time 1.07 seconds
Started May 02 02:52:16 PM PDT 24
Finished May 02 02:52:18 PM PDT 24
Peak memory 217924 kb
Host smart-6fb3808c-7207-4a24-8f29-0f02b1884c9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542955682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1542955682
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1660482572
Short name T74
Test name
Test status
Simulation time 19732222 ps
CPU time 1.1 seconds
Started May 02 02:52:10 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 218300 kb
Host smart-199bc3e7-4d7c-4eca-aedb-2b6b5263959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660482572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1660482572
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1224083511
Short name T687
Test name
Test status
Simulation time 152591500 ps
CPU time 1.4 seconds
Started May 02 02:52:09 PM PDT 24
Finished May 02 02:52:12 PM PDT 24
Peak memory 218340 kb
Host smart-98491698-41a5-4859-9e71-3c93e41a619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224083511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1224083511
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3724278978
Short name T392
Test name
Test status
Simulation time 28828466 ps
CPU time 0.94 seconds
Started May 02 02:52:05 PM PDT 24
Finished May 02 02:52:07 PM PDT 24
Peak memory 215220 kb
Host smart-ed717d5b-52ad-41c9-8bb0-8e8eb6e2b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724278978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3724278978
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.115517186
Short name T449
Test name
Test status
Simulation time 16625349 ps
CPU time 0.93 seconds
Started May 02 02:52:06 PM PDT 24
Finished May 02 02:52:08 PM PDT 24
Peak memory 215156 kb
Host smart-1ca24296-2f7a-4b2d-89b9-2029c6923b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115517186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.115517186
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1385621784
Short name T752
Test name
Test status
Simulation time 108951123 ps
CPU time 2.51 seconds
Started May 02 02:52:05 PM PDT 24
Finished May 02 02:52:09 PM PDT 24
Peak memory 217996 kb
Host smart-5ac95549-8739-4899-8e1c-da324d60dbcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385621784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1385621784
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_genbits.1995879011
Short name T81
Test name
Test status
Simulation time 38544249 ps
CPU time 1.55 seconds
Started May 02 02:54:03 PM PDT 24
Finished May 02 02:54:06 PM PDT 24
Peak memory 217964 kb
Host smart-1eba67a3-49c6-4e29-8300-6c72b6a2e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995879011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1995879011
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.4031872968
Short name T579
Test name
Test status
Simulation time 95189038 ps
CPU time 1.42 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 218288 kb
Host smart-07bcdd35-552d-43cb-9089-8e6625947efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031872968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4031872968
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3969815513
Short name T406
Test name
Test status
Simulation time 38457115 ps
CPU time 1.55 seconds
Started May 02 02:54:09 PM PDT 24
Finished May 02 02:54:12 PM PDT 24
Peak memory 217992 kb
Host smart-2a78f6d5-da82-4700-82b0-28f6ff084442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969815513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3969815513
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.953222848
Short name T619
Test name
Test status
Simulation time 42437615 ps
CPU time 1.19 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 218268 kb
Host smart-336641bd-c1f0-411c-8c1e-43b41f837e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953222848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.953222848
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1124946264
Short name T437
Test name
Test status
Simulation time 59006156 ps
CPU time 1.25 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 217956 kb
Host smart-66267fda-7976-40f3-9b62-47917ad54236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124946264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1124946264
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1048919898
Short name T777
Test name
Test status
Simulation time 80905334 ps
CPU time 1.12 seconds
Started May 02 02:54:05 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 216872 kb
Host smart-fdbbd2f9-0851-4ea4-9692-8e51855f58e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048919898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1048919898
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2980303394
Short name T465
Test name
Test status
Simulation time 48385942 ps
CPU time 1.74 seconds
Started May 02 02:54:09 PM PDT 24
Finished May 02 02:54:12 PM PDT 24
Peak memory 217932 kb
Host smart-4697bb20-0f7c-4392-9d70-1f9d96d67d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980303394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2980303394
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2745984395
Short name T514
Test name
Test status
Simulation time 64764182 ps
CPU time 1.55 seconds
Started May 02 02:54:05 PM PDT 24
Finished May 02 02:54:08 PM PDT 24
Peak memory 218300 kb
Host smart-535948ed-a718-452b-a7fd-130a1517e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745984395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2745984395
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1902038230
Short name T61
Test name
Test status
Simulation time 90792566 ps
CPU time 1.3 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:07 PM PDT 24
Peak memory 216828 kb
Host smart-81a2bc97-ad41-4be6-a4df-767fb14effa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902038230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1902038230
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2083330690
Short name T311
Test name
Test status
Simulation time 55635633 ps
CPU time 1.13 seconds
Started May 02 02:54:04 PM PDT 24
Finished May 02 02:54:06 PM PDT 24
Peak memory 218044 kb
Host smart-b21709fd-4acd-4982-aebb-9c8f406bf60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083330690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2083330690
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.4066160573
Short name T686
Test name
Test status
Simulation time 82003375 ps
CPU time 1.12 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:18 PM PDT 24
Peak memory 215552 kb
Host smart-bd42d333-a2fc-4e6d-8ce5-3057b08e85aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066160573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.4066160573
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3586181805
Short name T447
Test name
Test status
Simulation time 28803805 ps
CPU time 0.94 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:52:16 PM PDT 24
Peak memory 215052 kb
Host smart-a41887ec-7b77-439c-88e6-41907b641228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586181805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3586181805
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_err.908266890
Short name T124
Test name
Test status
Simulation time 20103423 ps
CPU time 1.17 seconds
Started May 02 02:52:17 PM PDT 24
Finished May 02 02:52:19 PM PDT 24
Peak memory 223908 kb
Host smart-4b19cb0f-3031-4d76-83ef-5d85f657ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908266890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.908266890
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2761579880
Short name T299
Test name
Test status
Simulation time 108632777 ps
CPU time 2.48 seconds
Started May 02 02:52:17 PM PDT 24
Finished May 02 02:52:20 PM PDT 24
Peak memory 219884 kb
Host smart-1846203f-1143-48b2-ada7-bb47b0bb8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761579880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2761579880
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2125842133
Short name T30
Test name
Test status
Simulation time 24602194 ps
CPU time 0.97 seconds
Started May 02 02:52:12 PM PDT 24
Finished May 02 02:52:14 PM PDT 24
Peak memory 215792 kb
Host smart-27404965-3178-42b0-8376-f5ecb265595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125842133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2125842133
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3103571236
Short name T651
Test name
Test status
Simulation time 21525467 ps
CPU time 0.93 seconds
Started May 02 02:52:13 PM PDT 24
Finished May 02 02:52:15 PM PDT 24
Peak memory 215160 kb
Host smart-4ec04bfb-9554-4d20-9c1c-88d4d241823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103571236 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3103571236
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2821389171
Short name T759
Test name
Test status
Simulation time 167459236 ps
CPU time 2.23 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:19 PM PDT 24
Peak memory 215176 kb
Host smart-085ff4c7-46e6-49dd-8e27-4ef7ad7dca16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821389171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2821389171
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1018069798
Short name T674
Test name
Test status
Simulation time 13495123146 ps
CPU time 350.25 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:58:06 PM PDT 24
Peak memory 218216 kb
Host smart-d00842ca-c7a0-4271-bf82-f858568c05f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018069798 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1018069798
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2326240646
Short name T356
Test name
Test status
Simulation time 42558057 ps
CPU time 1.75 seconds
Started May 02 02:54:05 PM PDT 24
Finished May 02 02:54:09 PM PDT 24
Peak memory 218132 kb
Host smart-50e1b92f-0d11-46af-b844-9999d85ac565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326240646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2326240646
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.4176903883
Short name T813
Test name
Test status
Simulation time 1040646591 ps
CPU time 7.75 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 219864 kb
Host smart-22e23843-3d85-4532-acd6-bbb13d6478ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176903883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4176903883
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.522909369
Short name T828
Test name
Test status
Simulation time 36889880 ps
CPU time 1.47 seconds
Started May 02 02:54:02 PM PDT 24
Finished May 02 02:54:05 PM PDT 24
Peak memory 218220 kb
Host smart-673c0923-0a3e-46e8-9a49-1dba4bf2df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522909369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.522909369
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1484634333
Short name T692
Test name
Test status
Simulation time 34462349 ps
CPU time 1.05 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 215152 kb
Host smart-3c72a5b1-d0b2-4db6-a162-ffb5786ad029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484634333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1484634333
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4220887560
Short name T374
Test name
Test status
Simulation time 37571339 ps
CPU time 1.56 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:14 PM PDT 24
Peak memory 218416 kb
Host smart-60a54c2c-3584-4228-b6b0-9920e9987936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220887560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4220887560
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1864642960
Short name T359
Test name
Test status
Simulation time 42328968 ps
CPU time 1.25 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 219508 kb
Host smart-8241f71b-aba3-4501-9aeb-5fcd4da64a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864642960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1864642960
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.2578649126
Short name T521
Test name
Test status
Simulation time 30061972 ps
CPU time 1.04 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 219392 kb
Host smart-0da3d15f-309a-467a-b0ff-6d3c36efe615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578649126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2578649126
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1652291988
Short name T636
Test name
Test status
Simulation time 30112786 ps
CPU time 1.33 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 217956 kb
Host smart-7d0b32ef-5417-441f-9a0e-4565074d4889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652291988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1652291988
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3585041654
Short name T265
Test name
Test status
Simulation time 105670102 ps
CPU time 1.29 seconds
Started May 02 02:52:16 PM PDT 24
Finished May 02 02:52:19 PM PDT 24
Peak memory 215560 kb
Host smart-179b2799-7333-430a-9b81-826ddfd5fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585041654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3585041654
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4257073230
Short name T407
Test name
Test status
Simulation time 55004879 ps
CPU time 0.79 seconds
Started May 02 02:52:13 PM PDT 24
Finished May 02 02:52:15 PM PDT 24
Peak memory 206324 kb
Host smart-e0334432-f0cb-45f1-84d1-baea7c03d7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257073230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4257073230
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.541172207
Short name T654
Test name
Test status
Simulation time 11435342 ps
CPU time 0.87 seconds
Started May 02 02:52:16 PM PDT 24
Finished May 02 02:52:18 PM PDT 24
Peak memory 216056 kb
Host smart-cc94f328-4b21-49d9-b2bf-e0d887a936a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541172207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.541172207
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2247548736
Short name T615
Test name
Test status
Simulation time 22910315 ps
CPU time 1.01 seconds
Started May 02 02:52:13 PM PDT 24
Finished May 02 02:52:15 PM PDT 24
Peak memory 219252 kb
Host smart-5c63439d-f914-4c66-8598-b357d978663d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247548736 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2247548736
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2209143520
Short name T368
Test name
Test status
Simulation time 23546767 ps
CPU time 1.14 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:17 PM PDT 24
Peak memory 218316 kb
Host smart-43dc3a7d-61b9-43cf-9503-b0efbe3d1834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209143520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2209143520
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4219422841
Short name T486
Test name
Test status
Simulation time 42367069 ps
CPU time 1.45 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:52:16 PM PDT 24
Peak memory 217940 kb
Host smart-d4a6722c-f6e9-4e72-9b85-cf58cc92bde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219422841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4219422841
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.766060533
Short name T154
Test name
Test status
Simulation time 32437891 ps
CPU time 0.94 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:52:16 PM PDT 24
Peak memory 223716 kb
Host smart-25e1aeb6-1ae0-45a9-9158-938bc857edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766060533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.766060533
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1474479331
Short name T365
Test name
Test status
Simulation time 49399536 ps
CPU time 1.01 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:17 PM PDT 24
Peak memory 215152 kb
Host smart-30c77bc7-2f67-472e-919a-5aecb8ad765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474479331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1474479331
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.402275820
Short name T638
Test name
Test status
Simulation time 149914276 ps
CPU time 2.32 seconds
Started May 02 02:52:18 PM PDT 24
Finished May 02 02:52:21 PM PDT 24
Peak memory 218228 kb
Host smart-d2a8b08c-377b-4d1e-86e8-5e858e86d13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402275820 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.402275820
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1504386097
Short name T697
Test name
Test status
Simulation time 76760041496 ps
CPU time 424.35 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:59:20 PM PDT 24
Peak memory 218828 kb
Host smart-cac52f5e-6a38-4241-b68f-3a0004934022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504386097 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1504386097
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1405204331
Short name T303
Test name
Test status
Simulation time 53542217 ps
CPU time 1.46 seconds
Started May 02 02:54:09 PM PDT 24
Finished May 02 02:54:11 PM PDT 24
Peak memory 218204 kb
Host smart-647b1de3-5b6e-46f2-b156-ae8dc0018999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405204331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1405204331
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1676900604
Short name T534
Test name
Test status
Simulation time 33518516 ps
CPU time 1.17 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 216728 kb
Host smart-7d459d1a-9ec5-4598-8b0d-ac438312b641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676900604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1676900604
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4197377619
Short name T508
Test name
Test status
Simulation time 76816324 ps
CPU time 1.27 seconds
Started May 02 02:54:08 PM PDT 24
Finished May 02 02:54:10 PM PDT 24
Peak memory 218356 kb
Host smart-5b75a8c6-4e25-465b-a9a2-01406f70a9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197377619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4197377619
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.559251832
Short name T833
Test name
Test status
Simulation time 131796042 ps
CPU time 2.83 seconds
Started May 02 02:54:12 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 219156 kb
Host smart-cff891ab-2bba-43c5-b342-807f66e63157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559251832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.559251832
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2067334916
Short name T430
Test name
Test status
Simulation time 68083444 ps
CPU time 1.19 seconds
Started May 02 02:54:12 PM PDT 24
Finished May 02 02:54:15 PM PDT 24
Peak memory 218148 kb
Host smart-073832d2-671a-4f96-8710-539cf7b22e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067334916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2067334916
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2572845768
Short name T771
Test name
Test status
Simulation time 189231234 ps
CPU time 2.43 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 219736 kb
Host smart-fd98bbc8-cd6b-4a22-950e-0d88b989f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572845768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2572845768
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1316973049
Short name T714
Test name
Test status
Simulation time 63751043 ps
CPU time 1.28 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 217920 kb
Host smart-fdcb43c1-12b5-4c51-91e0-db0208efad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316973049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1316973049
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3572293886
Short name T776
Test name
Test status
Simulation time 123503208 ps
CPU time 1.17 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 216216 kb
Host smart-897eaf56-0c73-47b2-99d5-065d1a6073a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572293886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3572293886
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2851715884
Short name T652
Test name
Test status
Simulation time 48560503 ps
CPU time 1.84 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 219640 kb
Host smart-1d743fdd-8654-4069-9552-8e0c46d43576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851715884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2851715884
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1303511000
Short name T277
Test name
Test status
Simulation time 49992167 ps
CPU time 1.15 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:14 PM PDT 24
Peak memory 219424 kb
Host smart-8e30d50c-4612-452c-9983-5c01b43dfb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303511000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1303511000
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1017477255
Short name T164
Test name
Test status
Simulation time 47221356 ps
CPU time 1.27 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:34 PM PDT 24
Peak memory 215552 kb
Host smart-67613ea8-3c1e-43b2-b159-c769810ca2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017477255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1017477255
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3988898319
Short name T576
Test name
Test status
Simulation time 16673744 ps
CPU time 0.98 seconds
Started May 02 02:51:35 PM PDT 24
Finished May 02 02:51:37 PM PDT 24
Peak memory 214752 kb
Host smart-bb725384-6803-4278-a266-8821c5e83538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988898319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3988898319
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2505612538
Short name T70
Test name
Test status
Simulation time 156672552 ps
CPU time 1.05 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:34 PM PDT 24
Peak memory 217972 kb
Host smart-54554621-fb9f-44d3-a7b8-bf7e59036569
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505612538 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2505612538
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1699459827
Short name T734
Test name
Test status
Simulation time 58355471 ps
CPU time 0.96 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 218248 kb
Host smart-621bd434-1e7f-4e03-9a77-c59d5185df0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699459827 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1699459827
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3088024244
Short name T705
Test name
Test status
Simulation time 43523961 ps
CPU time 1.23 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 218220 kb
Host smart-603b61cd-877b-4289-b01d-5e95f4d966d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088024244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3088024244
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2571092315
Short name T43
Test name
Test status
Simulation time 21907479 ps
CPU time 1.18 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:34 PM PDT 24
Peak memory 223872 kb
Host smart-fefbe283-5eff-4373-86b9-5142cd26de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571092315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2571092315
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1179379763
Short name T741
Test name
Test status
Simulation time 34853828 ps
CPU time 0.86 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 02:51:26 PM PDT 24
Peak memory 206968 kb
Host smart-bd7d0de0-28d4-472e-bb83-1b3571901d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179379763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1179379763
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2751099130
Short name T56
Test name
Test status
Simulation time 403517670 ps
CPU time 4.71 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 235424 kb
Host smart-aeba64b9-811f-4d4d-81f0-814220f67cd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751099130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2751099130
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.338347499
Short name T790
Test name
Test status
Simulation time 133778334 ps
CPU time 0.91 seconds
Started May 02 02:51:24 PM PDT 24
Finished May 02 02:51:26 PM PDT 24
Peak memory 215056 kb
Host smart-2dc67a0d-0b02-4733-a375-eb90edb14b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338347499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.338347499
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.834707901
Short name T563
Test name
Test status
Simulation time 285204340 ps
CPU time 3.18 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:38 PM PDT 24
Peak memory 216928 kb
Host smart-6fabf2ec-5f63-4c4b-a88f-63bcf8655eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834707901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.834707901
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1215818159
Short name T542
Test name
Test status
Simulation time 58962186066 ps
CPU time 731.69 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 03:03:46 PM PDT 24
Peak memory 217984 kb
Host smart-8dfb0ad0-83de-4fb9-ac33-c8a67e9765ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215818159 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1215818159
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4262058558
Short name T795
Test name
Test status
Simulation time 47602485 ps
CPU time 1.13 seconds
Started May 02 02:52:16 PM PDT 24
Finished May 02 02:52:18 PM PDT 24
Peak memory 215556 kb
Host smart-e8b453ee-5e4c-4e26-b0d6-117fbfa7be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262058558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4262058558
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.577802034
Short name T538
Test name
Test status
Simulation time 14673743 ps
CPU time 0.87 seconds
Started May 02 02:52:24 PM PDT 24
Finished May 02 02:52:26 PM PDT 24
Peak memory 206488 kb
Host smart-a1402074-dafa-46d3-81cf-552ba181c94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577802034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.577802034
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3516745904
Short name T562
Test name
Test status
Simulation time 19370009 ps
CPU time 0.8 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 216056 kb
Host smart-22c8fabd-2069-4f3d-9b4b-9878715a4c4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516745904 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3516745904
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.163495366
Short name T325
Test name
Test status
Simulation time 35053447 ps
CPU time 0.97 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 217668 kb
Host smart-eee2d17f-a307-48cc-a079-205120b140d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163495366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.163495366
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2599066210
Short name T178
Test name
Test status
Simulation time 36448841 ps
CPU time 1.43 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 225368 kb
Host smart-a7af64b6-12f4-4c76-be61-00f9c7c61579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599066210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2599066210
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3851992949
Short name T608
Test name
Test status
Simulation time 32986543 ps
CPU time 1.26 seconds
Started May 02 02:52:14 PM PDT 24
Finished May 02 02:52:17 PM PDT 24
Peak memory 217940 kb
Host smart-db2df9d7-16dc-43de-a3eb-b0da40fd9482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851992949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3851992949
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.62028444
Short name T684
Test name
Test status
Simulation time 22470919 ps
CPU time 1.18 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:18 PM PDT 24
Peak memory 223892 kb
Host smart-6fa8b86e-404d-48b0-b1f5-04f1408f4523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62028444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.62028444
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1133120762
Short name T611
Test name
Test status
Simulation time 17680075 ps
CPU time 0.99 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:17 PM PDT 24
Peak memory 215160 kb
Host smart-62c4da03-98c8-41e3-b553-c554e43be352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133120762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1133120762
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3850230619
Short name T635
Test name
Test status
Simulation time 651921787 ps
CPU time 3.18 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 02:52:20 PM PDT 24
Peak memory 216732 kb
Host smart-1e39e729-ae60-48ff-a07d-371e34ad0fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850230619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3850230619
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2419303471
Short name T814
Test name
Test status
Simulation time 314732688883 ps
CPU time 2081.3 seconds
Started May 02 02:52:15 PM PDT 24
Finished May 02 03:26:58 PM PDT 24
Peak memory 229288 kb
Host smart-943056ea-7532-40f4-8b48-aba9c2422d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419303471 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2419303471
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1222734434
Short name T736
Test name
Test status
Simulation time 60040348 ps
CPU time 1.69 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:14 PM PDT 24
Peak memory 218216 kb
Host smart-4d4d49ff-95e6-40cd-912e-e73d0d4e2a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222734434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1222734434
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4102206069
Short name T298
Test name
Test status
Simulation time 84826704 ps
CPU time 2.83 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:18 PM PDT 24
Peak memory 218836 kb
Host smart-9e1f4cd0-a205-427c-aac2-ceed2efd3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102206069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4102206069
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.606569449
Short name T500
Test name
Test status
Simulation time 37644418 ps
CPU time 1.44 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 216972 kb
Host smart-c5935e2e-2a32-4671-b3b4-36b0b42213a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606569449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.606569449
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2787606730
Short name T463
Test name
Test status
Simulation time 91937221 ps
CPU time 1.1 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 216808 kb
Host smart-2e61d8f8-02d0-4beb-a406-6448db6f7439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787606730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2787606730
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2440882675
Short name T334
Test name
Test status
Simulation time 323861106 ps
CPU time 3.31 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 218744 kb
Host smart-fe78975b-3de6-4bd9-81de-e5a8f9997ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440882675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2440882675
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1087635333
Short name T282
Test name
Test status
Simulation time 184699405 ps
CPU time 1.9 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:14 PM PDT 24
Peak memory 218904 kb
Host smart-0042484b-b1a2-413d-bde2-8feeb4778f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087635333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1087635333
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2821606703
Short name T275
Test name
Test status
Simulation time 51124495 ps
CPU time 1.86 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 218244 kb
Host smart-afb8b23b-d478-4396-a622-cd4379a665cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821606703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2821606703
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.654184840
Short name T520
Test name
Test status
Simulation time 47290780 ps
CPU time 1.55 seconds
Started May 02 02:54:12 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 216952 kb
Host smart-3d7a91c2-c9f9-4479-b09b-97b8808d2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654184840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.654184840
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4110150783
Short name T400
Test name
Test status
Simulation time 86850002 ps
CPU time 1.39 seconds
Started May 02 02:54:15 PM PDT 24
Finished May 02 02:54:18 PM PDT 24
Peak memory 216864 kb
Host smart-668c4a3a-5673-4421-abe4-a5b96970a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110150783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4110150783
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.804427999
Short name T480
Test name
Test status
Simulation time 27825310 ps
CPU time 1.05 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 218324 kb
Host smart-e807b4fd-7235-4f72-be25-5ca4f0c663fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804427999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.804427999
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.1391956458
Short name T830
Test name
Test status
Simulation time 63523500 ps
CPU time 0.96 seconds
Started May 02 02:52:18 PM PDT 24
Finished May 02 02:52:20 PM PDT 24
Peak memory 215032 kb
Host smart-2cdafeec-7349-43d4-9e8d-762efecfe700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391956458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1391956458
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1283876800
Short name T88
Test name
Test status
Simulation time 22481926 ps
CPU time 0.88 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:23 PM PDT 24
Peak memory 216156 kb
Host smart-c05dd115-0afd-498d-b0ac-d185803d3459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283876800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1283876800
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.161232205
Short name T110
Test name
Test status
Simulation time 31706297 ps
CPU time 1.22 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 219312 kb
Host smart-b92c06cb-3a7a-411d-b2a8-304677a4bf96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161232205 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.161232205
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1621329253
Short name T399
Test name
Test status
Simulation time 23696499 ps
CPU time 0.94 seconds
Started May 02 02:52:24 PM PDT 24
Finished May 02 02:52:26 PM PDT 24
Peak memory 218088 kb
Host smart-78d77508-1d82-4e03-96c0-3655f6a148e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621329253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1621329253
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.857547073
Short name T728
Test name
Test status
Simulation time 90075322 ps
CPU time 3.18 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 219644 kb
Host smart-ed1ba8ca-0102-4de5-926a-8c8b059b5f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857547073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.857547073
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1477285464
Short name T698
Test name
Test status
Simulation time 30997414 ps
CPU time 0.83 seconds
Started May 02 02:52:17 PM PDT 24
Finished May 02 02:52:19 PM PDT 24
Peak memory 215108 kb
Host smart-6f2f3f83-49f6-440d-9c5b-afc0850891d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477285464 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1477285464
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3329036811
Short name T746
Test name
Test status
Simulation time 26082823 ps
CPU time 0.97 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 215168 kb
Host smart-e56dd989-5f08-4ebe-921a-9862e3accfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329036811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3329036811
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.342662394
Short name T381
Test name
Test status
Simulation time 174041923 ps
CPU time 3.67 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 215180 kb
Host smart-4e7ae4e0-232a-4b04-b713-86411051e220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342662394 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.342662394
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.850599792
Short name T678
Test name
Test status
Simulation time 91569451599 ps
CPU time 2193.11 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 03:28:54 PM PDT 24
Peak memory 230784 kb
Host smart-3db4987d-ac8a-446c-afe1-38581c013a31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850599792 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.850599792
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3112032719
Short name T763
Test name
Test status
Simulation time 197509191 ps
CPU time 1.64 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:12 PM PDT 24
Peak memory 218280 kb
Host smart-a3622190-d42c-48f4-9200-32785937c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112032719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3112032719
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1852183987
Short name T295
Test name
Test status
Simulation time 243474997 ps
CPU time 1.7 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 218208 kb
Host smart-1be30a25-0227-4dc0-83fb-4185eee6b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852183987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1852183987
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.837394100
Short name T727
Test name
Test status
Simulation time 55202507 ps
CPU time 1.24 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 218308 kb
Host smart-5c63474f-e91e-461e-82a8-d6c670bab3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837394100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.837394100
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1003627075
Short name T301
Test name
Test status
Simulation time 77651735 ps
CPU time 1.32 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 218316 kb
Host smart-e36a8778-563a-41b3-8fcf-29e841d8f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003627075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1003627075
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1872747557
Short name T555
Test name
Test status
Simulation time 59172283 ps
CPU time 1.32 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 218140 kb
Host smart-002c5f39-c129-4190-9fd6-0b747cbee10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872747557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1872747557
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3343647262
Short name T495
Test name
Test status
Simulation time 41693799 ps
CPU time 1.44 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 217976 kb
Host smart-03eab9e7-f766-4ec9-86ef-8cbe29d95681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343647262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3343647262
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.589554056
Short name T663
Test name
Test status
Simulation time 143442013 ps
CPU time 1.22 seconds
Started May 02 02:54:19 PM PDT 24
Finished May 02 02:54:22 PM PDT 24
Peak memory 219720 kb
Host smart-755240ea-36e8-48d0-a97d-30b3798bd2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589554056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.589554056
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4181812828
Short name T331
Test name
Test status
Simulation time 76782920 ps
CPU time 1.66 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 219308 kb
Host smart-47071b43-5077-4129-a371-a6bcef5dab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181812828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4181812828
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.61749369
Short name T443
Test name
Test status
Simulation time 31428562 ps
CPU time 1.1 seconds
Started May 02 02:54:11 PM PDT 24
Finished May 02 02:54:14 PM PDT 24
Peak memory 216828 kb
Host smart-f456c3ca-7262-4eda-a89b-a447e451dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61749369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.61749369
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3833358024
Short name T708
Test name
Test status
Simulation time 76270125 ps
CPU time 1.22 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 215560 kb
Host smart-8dfd9cad-6428-45c2-832d-d654c5938bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833358024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3833358024
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.178938591
Short name T442
Test name
Test status
Simulation time 23547900 ps
CPU time 0.86 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 215068 kb
Host smart-a428497b-7410-45a4-b471-dcb646ce74b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178938591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.178938591
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3069043111
Short name T45
Test name
Test status
Simulation time 33441678 ps
CPU time 1.16 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:23 PM PDT 24
Peak memory 216644 kb
Host smart-f2d99d91-275b-4fd6-91e9-c1d96857bcb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069043111 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3069043111
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2990023039
Short name T385
Test name
Test status
Simulation time 41722958 ps
CPU time 0.97 seconds
Started May 02 02:52:22 PM PDT 24
Finished May 02 02:52:25 PM PDT 24
Peak memory 223672 kb
Host smart-aff7a534-f77e-49df-bd8b-9986c945f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990023039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2990023039
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3363596018
Short name T650
Test name
Test status
Simulation time 35410584 ps
CPU time 1.04 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:21 PM PDT 24
Peak memory 216840 kb
Host smart-2c7332a9-ddbb-47ae-a437-828ba3afddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363596018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3363596018
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3303674634
Short name T167
Test name
Test status
Simulation time 25067597 ps
CPU time 0.93 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 215636 kb
Host smart-c64db8df-e528-432f-b811-5cc8bf15ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303674634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3303674634
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.575976839
Short name T722
Test name
Test status
Simulation time 18482346 ps
CPU time 1.01 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:21 PM PDT 24
Peak memory 215172 kb
Host smart-0753dd07-8ac5-42ca-a4bb-26da60aca93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575976839 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.575976839
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.849560183
Short name T338
Test name
Test status
Simulation time 45155102 ps
CPU time 1.49 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:21 PM PDT 24
Peak memory 215060 kb
Host smart-25f1960f-4067-478a-8bba-3c5a905112f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849560183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.849560183
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2907600866
Short name T794
Test name
Test status
Simulation time 52210974955 ps
CPU time 313.39 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:57:34 PM PDT 24
Peak memory 218088 kb
Host smart-be43cb22-292a-4093-91c8-45da71506711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907600866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2907600866
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.387920904
Short name T621
Test name
Test status
Simulation time 38247412 ps
CPU time 1.74 seconds
Started May 02 02:54:10 PM PDT 24
Finished May 02 02:54:13 PM PDT 24
Peak memory 216968 kb
Host smart-94ad9465-1768-43c5-b4d6-d1b189b16e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387920904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.387920904
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2942135086
Short name T593
Test name
Test status
Simulation time 50588596 ps
CPU time 1.58 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 218068 kb
Host smart-b76cf314-b652-4dbd-9593-cb041609b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942135086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2942135086
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1286453340
Short name T699
Test name
Test status
Simulation time 84611253 ps
CPU time 1.09 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 216904 kb
Host smart-d907f83c-65df-4eba-a82a-f898766c1781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286453340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1286453340
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.554562651
Short name T829
Test name
Test status
Simulation time 85346374 ps
CPU time 1.28 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 218416 kb
Host smart-c3263460-40a5-4df8-9884-bfc766ac1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554562651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.554562651
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4032046874
Short name T571
Test name
Test status
Simulation time 100910351 ps
CPU time 1.19 seconds
Started May 02 02:54:13 PM PDT 24
Finished May 02 02:54:16 PM PDT 24
Peak memory 218416 kb
Host smart-02b86d04-8440-4fbb-9aad-b3bb862cbbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032046874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4032046874
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3729482126
Short name T634
Test name
Test status
Simulation time 58216728 ps
CPU time 1.55 seconds
Started May 02 02:54:14 PM PDT 24
Finished May 02 02:54:17 PM PDT 24
Peak memory 218204 kb
Host smart-c312db3a-9b5f-492b-9b84-b339ba5c9486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729482126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3729482126
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.905094348
Short name T596
Test name
Test status
Simulation time 60136060 ps
CPU time 1.32 seconds
Started May 02 02:54:22 PM PDT 24
Finished May 02 02:54:24 PM PDT 24
Peak memory 218084 kb
Host smart-36071fdb-83c4-4899-8501-22e7e0248270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905094348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.905094348
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2543341985
Short name T772
Test name
Test status
Simulation time 252088176 ps
CPU time 2.07 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 219768 kb
Host smart-18730700-33d9-49e9-88eb-31166f052915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543341985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2543341985
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2092247110
Short name T691
Test name
Test status
Simulation time 82192152 ps
CPU time 1.11 seconds
Started May 02 02:54:21 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 217960 kb
Host smart-a9ad2cd8-8c61-428f-ae43-ac4752082678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092247110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2092247110
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.527543951
Short name T408
Test name
Test status
Simulation time 37945287 ps
CPU time 1.34 seconds
Started May 02 02:54:16 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 217908 kb
Host smart-d6ea7ece-aa0c-4cd5-8229-e05dc9fc2092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527543951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.527543951
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1591722344
Short name T189
Test name
Test status
Simulation time 93255769 ps
CPU time 1.23 seconds
Started May 02 02:52:18 PM PDT 24
Finished May 02 02:52:20 PM PDT 24
Peak memory 215468 kb
Host smart-880da929-311e-425b-9752-d5f5412affb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591722344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1591722344
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.34519027
Short name T647
Test name
Test status
Simulation time 15815407 ps
CPU time 0.93 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 206488 kb
Host smart-319696e9-1d59-4429-8a12-102c30b8b976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34519027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.34519027
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.189402838
Short name T450
Test name
Test status
Simulation time 23331480 ps
CPU time 0.83 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 216196 kb
Host smart-218b2fbd-fbfe-4988-9c39-7427f8a82a99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189402838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.189402838
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4027781672
Short name T640
Test name
Test status
Simulation time 36975002 ps
CPU time 1.29 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:24 PM PDT 24
Peak memory 218108 kb
Host smart-36685640-beee-466f-b14b-f7f9cc44295c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027781672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4027781672
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1717780640
Short name T140
Test name
Test status
Simulation time 43273734 ps
CPU time 0.86 seconds
Started May 02 02:52:21 PM PDT 24
Finished May 02 02:52:23 PM PDT 24
Peak memory 218120 kb
Host smart-83530d08-351b-442b-abf4-62c590fae361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717780640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1717780640
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3564611698
Short name T832
Test name
Test status
Simulation time 29304552 ps
CPU time 1.28 seconds
Started May 02 02:52:24 PM PDT 24
Finished May 02 02:52:27 PM PDT 24
Peak memory 218068 kb
Host smart-e20350a1-3bee-483b-9c8d-0aafade05217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564611698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3564611698
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3741382721
Short name T370
Test name
Test status
Simulation time 38046026 ps
CPU time 0.9 seconds
Started May 02 02:52:19 PM PDT 24
Finished May 02 02:52:22 PM PDT 24
Peak memory 215084 kb
Host smart-8d019115-f893-421e-9776-387d1a300a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741382721 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3741382721
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2778225155
Short name T411
Test name
Test status
Simulation time 28317919 ps
CPU time 0.92 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:23 PM PDT 24
Peak memory 215172 kb
Host smart-d273bbd2-3c97-4bcc-830a-051e2c836efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778225155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2778225155
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1920760769
Short name T214
Test name
Test status
Simulation time 182170139 ps
CPU time 1.78 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 02:52:23 PM PDT 24
Peak memory 216828 kb
Host smart-a78c2b98-4baf-46b5-8921-5d3ffc8f0f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920760769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1920760769
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3510767337
Short name T501
Test name
Test status
Simulation time 59059790914 ps
CPU time 1283.72 seconds
Started May 02 02:52:20 PM PDT 24
Finished May 02 03:13:45 PM PDT 24
Peak memory 221412 kb
Host smart-7657ebdf-85bf-4bd8-8f20-3c91657f7476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510767337 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3510767337
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4043039927
Short name T589
Test name
Test status
Simulation time 46382089 ps
CPU time 0.97 seconds
Started May 02 02:54:19 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 216960 kb
Host smart-f6758326-1ee6-41ed-893f-3e4dd8d3187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043039927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4043039927
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.48685992
Short name T284
Test name
Test status
Simulation time 72362035 ps
CPU time 1.48 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:20 PM PDT 24
Peak memory 218300 kb
Host smart-691e1a6c-3f9a-438d-8969-c1fedb32f0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48685992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.48685992
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.149283809
Short name T62
Test name
Test status
Simulation time 68228820 ps
CPU time 1.13 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 218920 kb
Host smart-5ad7b9fd-1fa5-47a4-8202-d3ab141e23c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149283809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.149283809
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3795472830
Short name T703
Test name
Test status
Simulation time 61100225 ps
CPU time 1.35 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 218152 kb
Host smart-6a8e46fa-da07-4557-9fc6-b43cde6a0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795472830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3795472830
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1811972009
Short name T317
Test name
Test status
Simulation time 90989839 ps
CPU time 1.53 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 218428 kb
Host smart-1d4188b3-c5a7-4457-9233-b8b823f70199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811972009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1811972009
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4151669393
Short name T541
Test name
Test status
Simulation time 68686130 ps
CPU time 1.51 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 218216 kb
Host smart-c1608a32-0d6a-4c0c-80cf-9ccaf41dc67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151669393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4151669393
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3972000469
Short name T404
Test name
Test status
Simulation time 51207641 ps
CPU time 1.34 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 219488 kb
Host smart-a5f5d636-14e0-4631-91b4-d1c88914147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972000469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3972000469
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.233252014
Short name T73
Test name
Test status
Simulation time 93854984 ps
CPU time 1.5 seconds
Started May 02 02:54:16 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 218356 kb
Host smart-a147900d-74b5-4a9b-a468-1820416a82f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233252014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.233252014
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.112390928
Short name T427
Test name
Test status
Simulation time 116272367 ps
CPU time 1.21 seconds
Started May 02 02:54:19 PM PDT 24
Finished May 02 02:54:22 PM PDT 24
Peak memory 217172 kb
Host smart-a33ad7a7-99c5-4f53-9644-5725d6fdcc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112390928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.112390928
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1797564490
Short name T216
Test name
Test status
Simulation time 41852694 ps
CPU time 1.37 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 215184 kb
Host smart-9829e6cb-20f9-4880-b1df-1efe6a1e7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797564490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1797564490
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4219423418
Short name T645
Test name
Test status
Simulation time 22590524 ps
CPU time 1.23 seconds
Started May 02 02:52:29 PM PDT 24
Finished May 02 02:52:31 PM PDT 24
Peak memory 215508 kb
Host smart-1320dd56-c1f0-4b56-950a-41c098e4e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219423418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4219423418
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4106565290
Short name T529
Test name
Test status
Simulation time 23749084 ps
CPU time 0.91 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 02:52:30 PM PDT 24
Peak memory 206072 kb
Host smart-e3ff4604-ca32-463d-b210-fbb1a4e418e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106565290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4106565290
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3474471188
Short name T125
Test name
Test status
Simulation time 21534896 ps
CPU time 0.84 seconds
Started May 02 02:52:27 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 215256 kb
Host smart-ba707fe1-bebb-4c44-93dd-5ab5544b9780
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474471188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3474471188
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.676823712
Short name T770
Test name
Test status
Simulation time 248112842 ps
CPU time 1.21 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 02:52:31 PM PDT 24
Peak memory 216788 kb
Host smart-8aa1254e-638b-42b3-ae5e-566a56ec7624
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676823712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.676823712
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1754216005
Short name T101
Test name
Test status
Simulation time 53381460 ps
CPU time 1.03 seconds
Started May 02 02:52:26 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 220448 kb
Host smart-426109b1-24ea-449c-b675-669895c06fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754216005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1754216005
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1678818762
Short name T468
Test name
Test status
Simulation time 52633230 ps
CPU time 1.84 seconds
Started May 02 02:52:27 PM PDT 24
Finished May 02 02:52:30 PM PDT 24
Peak memory 218084 kb
Host smart-6f11298d-dce2-4f1d-b83b-08e870c0810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678818762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1678818762
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.905220809
Short name T720
Test name
Test status
Simulation time 21260011 ps
CPU time 1.11 seconds
Started May 02 02:52:27 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 215316 kb
Host smart-6a4158eb-e353-4666-b22e-43c99a0b4615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905220809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.905220809
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2429361012
Short name T820
Test name
Test status
Simulation time 45717446 ps
CPU time 0.93 seconds
Started May 02 02:52:24 PM PDT 24
Finished May 02 02:52:26 PM PDT 24
Peak memory 215132 kb
Host smart-0e497c87-7f15-449f-b76f-6a48fcbd0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429361012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2429361012
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3748069947
Short name T318
Test name
Test status
Simulation time 17232345 ps
CPU time 0.92 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 206132 kb
Host smart-c59ed3d6-e23d-4dba-8668-b0ce1a4e6970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748069947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3748069947
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4101117789
Short name T554
Test name
Test status
Simulation time 52424096181 ps
CPU time 650.49 seconds
Started May 02 02:52:26 PM PDT 24
Finished May 02 03:03:18 PM PDT 24
Peak memory 218292 kb
Host smart-aac82a04-049c-44d4-8c00-d67cec60090f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101117789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4101117789
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/241.edn_genbits.2440377601
Short name T494
Test name
Test status
Simulation time 75028792 ps
CPU time 1.22 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:20 PM PDT 24
Peak memory 218008 kb
Host smart-97e9c9e3-caec-4f0b-8cd5-8b0f73702f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440377601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2440377601
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1780527419
Short name T271
Test name
Test status
Simulation time 45051703 ps
CPU time 0.98 seconds
Started May 02 02:54:19 PM PDT 24
Finished May 02 02:54:22 PM PDT 24
Peak memory 216820 kb
Host smart-61a4dc81-8276-41d5-939a-ada2e8bd58c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780527419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1780527419
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3402771371
Short name T293
Test name
Test status
Simulation time 36482132 ps
CPU time 1.31 seconds
Started May 02 02:54:19 PM PDT 24
Finished May 02 02:54:22 PM PDT 24
Peak memory 216832 kb
Host smart-f5b7c9ae-627e-4702-844b-a64872ceb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402771371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3402771371
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2540804494
Short name T470
Test name
Test status
Simulation time 73383960 ps
CPU time 1.1 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 217092 kb
Host smart-141d3884-f931-4bb3-8cd6-433d9c6f0edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540804494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2540804494
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1484966089
Short name T572
Test name
Test status
Simulation time 32571237 ps
CPU time 1.24 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 216784 kb
Host smart-36232b4b-169b-483a-a74a-78805f488d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484966089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1484966089
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.61806835
Short name T735
Test name
Test status
Simulation time 42867177 ps
CPU time 1.46 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 217904 kb
Host smart-e3bdc43b-37bc-42d3-8d00-7b136ff0e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61806835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.61806835
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1131505093
Short name T380
Test name
Test status
Simulation time 65826048 ps
CPU time 1.33 seconds
Started May 02 02:54:22 PM PDT 24
Finished May 02 02:54:25 PM PDT 24
Peak memory 218344 kb
Host smart-9f2f91f0-2550-4d9a-a434-a2b367f1f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131505093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1131505093
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2376036892
Short name T617
Test name
Test status
Simulation time 159108339 ps
CPU time 1 seconds
Started May 02 02:54:21 PM PDT 24
Finished May 02 02:54:24 PM PDT 24
Peak memory 217016 kb
Host smart-503495de-9282-4c00-9d9a-3e98809af56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376036892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2376036892
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.4124833933
Short name T382
Test name
Test status
Simulation time 29420737 ps
CPU time 1.42 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 218288 kb
Host smart-0ccc4ac1-6d0f-4a89-aa12-08983c4f36ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124833933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4124833933
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2185889951
Short name T822
Test name
Test status
Simulation time 90873960 ps
CPU time 1.2 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 02:52:31 PM PDT 24
Peak memory 215536 kb
Host smart-e606b34e-a66a-46d0-8784-892bb83ed0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185889951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2185889951
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.4187341814
Short name T546
Test name
Test status
Simulation time 42692831 ps
CPU time 0.9 seconds
Started May 02 02:52:29 PM PDT 24
Finished May 02 02:52:31 PM PDT 24
Peak memory 214580 kb
Host smart-da1b7a9e-b224-4c3e-955f-ad26ae5d29b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187341814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4187341814
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2557434151
Short name T146
Test name
Test status
Simulation time 30519367 ps
CPU time 0.91 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 02:52:30 PM PDT 24
Peak memory 216160 kb
Host smart-760a0dae-de05-4175-86d8-d63faba0ca58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557434151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2557434151
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.2040558896
Short name T656
Test name
Test status
Simulation time 33297202 ps
CPU time 1.17 seconds
Started May 02 02:52:25 PM PDT 24
Finished May 02 02:52:28 PM PDT 24
Peak memory 223648 kb
Host smart-5841ec7c-aab8-466a-bcaf-827818935767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040558896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2040558896
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3471427950
Short name T315
Test name
Test status
Simulation time 91092326 ps
CPU time 1.14 seconds
Started May 02 02:52:26 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 216740 kb
Host smart-aa44018b-8d8b-4f4d-b64f-9299f27b3ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471427950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3471427950
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3048498614
Short name T53
Test name
Test status
Simulation time 23904554 ps
CPU time 1.18 seconds
Started May 02 02:52:25 PM PDT 24
Finished May 02 02:52:28 PM PDT 24
Peak memory 223908 kb
Host smart-3de5a21b-a5f8-436d-a25a-25cbc937fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048498614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3048498614
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2021616001
Short name T341
Test name
Test status
Simulation time 49225623 ps
CPU time 0.95 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 02:52:30 PM PDT 24
Peak memory 214648 kb
Host smart-0818d479-6f49-4c60-8a7b-64a094a0b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021616001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2021616001
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3072955114
Short name T410
Test name
Test status
Simulation time 603619222 ps
CPU time 1.9 seconds
Started May 02 02:52:25 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 216852 kb
Host smart-821d61a9-aad1-4f9f-ae29-d0cc742fe00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072955114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3072955114
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2771313127
Short name T585
Test name
Test status
Simulation time 60249086088 ps
CPU time 719.06 seconds
Started May 02 02:52:28 PM PDT 24
Finished May 02 03:04:28 PM PDT 24
Peak memory 218256 kb
Host smart-c41b20cd-209b-46df-b21e-d1457383aa6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771313127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2771313127
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.688388672
Short name T665
Test name
Test status
Simulation time 41709240 ps
CPU time 1.26 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:23 PM PDT 24
Peak memory 219212 kb
Host smart-29c9f71b-36ab-4989-87b9-90ad57aac7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688388672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.688388672
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.985739295
Short name T552
Test name
Test status
Simulation time 40865527 ps
CPU time 1.42 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 218292 kb
Host smart-ac73c005-0822-4390-b5cd-556ea21075f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985739295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.985739295
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.552747018
Short name T429
Test name
Test status
Simulation time 60908770 ps
CPU time 1.67 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:20 PM PDT 24
Peak memory 218400 kb
Host smart-97618ea5-629d-461a-b473-fb8e50fcd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552747018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.552747018
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3922054827
Short name T659
Test name
Test status
Simulation time 71084942 ps
CPU time 1.33 seconds
Started May 02 02:54:16 PM PDT 24
Finished May 02 02:54:19 PM PDT 24
Peak memory 218088 kb
Host smart-d6b012fc-3821-406d-89eb-2a21a6a361a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922054827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3922054827
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3273856097
Short name T578
Test name
Test status
Simulation time 58327046 ps
CPU time 1.25 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 217916 kb
Host smart-6169c5fb-45a8-4652-95ce-3fea10042700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273856097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3273856097
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2987787611
Short name T276
Test name
Test status
Simulation time 80087528 ps
CPU time 2.58 seconds
Started May 02 02:54:20 PM PDT 24
Finished May 02 02:54:25 PM PDT 24
Peak memory 219664 kb
Host smart-1a861e8c-b34d-4cd8-81f8-da6b51d5e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987787611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2987787611
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1055731867
Short name T815
Test name
Test status
Simulation time 102669010 ps
CPU time 1.53 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 218488 kb
Host smart-e7c5f3e8-34db-431a-a410-4abdbe92b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055731867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1055731867
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1671226490
Short name T662
Test name
Test status
Simulation time 44683437 ps
CPU time 1.17 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 217072 kb
Host smart-054ccb4e-0a89-479d-af65-48e577e077f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671226490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1671226490
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1995673269
Short name T424
Test name
Test status
Simulation time 101851223 ps
CPU time 2.85 seconds
Started May 02 02:54:18 PM PDT 24
Finished May 02 02:54:21 PM PDT 24
Peak memory 219792 kb
Host smart-a5a98355-58a2-429d-b29b-afc65df4ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995673269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1995673269
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2417015284
Short name T337
Test name
Test status
Simulation time 142500941 ps
CPU time 2.95 seconds
Started May 02 02:54:16 PM PDT 24
Finished May 02 02:54:20 PM PDT 24
Peak memory 219716 kb
Host smart-30ed6386-12d8-428e-8879-1506c62d4af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417015284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2417015284
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1764143342
Short name T267
Test name
Test status
Simulation time 26508726 ps
CPU time 1.19 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 215576 kb
Host smart-0fbf00f6-0d19-4c0c-b2ea-1da11eac134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764143342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1764143342
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.91208967
Short name T738
Test name
Test status
Simulation time 12865497 ps
CPU time 0.88 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:35 PM PDT 24
Peak memory 206960 kb
Host smart-4ffcfe60-3572-4c73-bcc1-dec9224e99da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91208967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.91208967
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.300120298
Short name T418
Test name
Test status
Simulation time 20186613 ps
CPU time 0.84 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 215764 kb
Host smart-99531099-942d-47b7-bc7a-95e60ffaccb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300120298 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.300120298
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4257866593
Short name T67
Test name
Test status
Simulation time 36951990 ps
CPU time 1.17 seconds
Started May 02 02:52:38 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 219360 kb
Host smart-5d535e97-8c7a-454b-b399-db171ed1a8c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257866593 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4257866593
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.376652133
Short name T176
Test name
Test status
Simulation time 19206118 ps
CPU time 1.04 seconds
Started May 02 02:52:34 PM PDT 24
Finished May 02 02:52:37 PM PDT 24
Peak memory 218348 kb
Host smart-6961a342-4bc2-45ba-80bf-8abe4b78533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376652133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.376652133
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3012960093
Short name T361
Test name
Test status
Simulation time 192793853 ps
CPU time 1.17 seconds
Started May 02 02:52:24 PM PDT 24
Finished May 02 02:52:27 PM PDT 24
Peak memory 216856 kb
Host smart-4bb669a2-d81d-4da3-890f-109412cceb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012960093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3012960093
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2658335246
Short name T481
Test name
Test status
Simulation time 20757261 ps
CPU time 1.23 seconds
Started May 02 02:52:26 PM PDT 24
Finished May 02 02:52:29 PM PDT 24
Peak memory 223888 kb
Host smart-18ca8287-d84d-48b7-a9fd-111a7466b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658335246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2658335246
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.633150622
Short name T204
Test name
Test status
Simulation time 18664281 ps
CPU time 1.06 seconds
Started May 02 02:52:27 PM PDT 24
Finished May 02 02:52:30 PM PDT 24
Peak memory 215128 kb
Host smart-25c759b2-6d65-499e-8891-7a619947a35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633150622 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.633150622
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.291478685
Short name T47
Test name
Test status
Simulation time 884854032 ps
CPU time 5.31 seconds
Started May 02 02:52:27 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 216768 kb
Host smart-ffe202a2-e8c1-40b6-92fe-a85b61ad4458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291478685 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.291478685
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3091410077
Short name T197
Test name
Test status
Simulation time 411735090562 ps
CPU time 2820.1 seconds
Started May 02 02:52:25 PM PDT 24
Finished May 02 03:39:26 PM PDT 24
Peak memory 232920 kb
Host smart-c3b8588a-e554-43f2-b187-9ecb50556df7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091410077 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3091410077
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1980935342
Short name T297
Test name
Test status
Simulation time 157653627 ps
CPU time 1.07 seconds
Started May 02 02:54:17 PM PDT 24
Finished May 02 02:54:20 PM PDT 24
Peak memory 216736 kb
Host smart-626e20ce-1cba-49fd-b2be-a51063cd36d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980935342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1980935342
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.835661565
Short name T37
Test name
Test status
Simulation time 86220736 ps
CPU time 1.38 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 218352 kb
Host smart-85924565-a17e-49ed-9af0-6750315197f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835661565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.835661565
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3464555391
Short name T567
Test name
Test status
Simulation time 181654051 ps
CPU time 1.21 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 216832 kb
Host smart-da13ab29-12f9-4707-bab1-b1036c41e863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464555391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3464555391
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1245300406
Short name T296
Test name
Test status
Simulation time 587076116 ps
CPU time 5.85 seconds
Started May 02 02:54:26 PM PDT 24
Finished May 02 02:54:33 PM PDT 24
Peak memory 217072 kb
Host smart-910bc6b1-632b-439d-b7d7-8b9189988922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245300406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1245300406
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1149691270
Short name T805
Test name
Test status
Simulation time 54739941 ps
CPU time 2.12 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 218092 kb
Host smart-8895d08c-3c5d-47be-837c-3f638de5a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149691270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1149691270
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3819396130
Short name T644
Test name
Test status
Simulation time 67242115 ps
CPU time 1.01 seconds
Started May 02 02:54:23 PM PDT 24
Finished May 02 02:54:25 PM PDT 24
Peak memory 218148 kb
Host smart-06aa0acf-14be-4452-86a0-f0b7cdbd7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819396130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3819396130
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1045362304
Short name T448
Test name
Test status
Simulation time 97830277 ps
CPU time 1.55 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:29 PM PDT 24
Peak memory 218640 kb
Host smart-c50dcf76-2f7a-4ea4-b519-bd2fdd856e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045362304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1045362304
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.165263954
Short name T788
Test name
Test status
Simulation time 33250031 ps
CPU time 1.33 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 218180 kb
Host smart-09412b1f-1dc3-4cea-9b29-fec064b1238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165263954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.165263954
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3928721121
Short name T440
Test name
Test status
Simulation time 100561769 ps
CPU time 1.65 seconds
Started May 02 02:54:23 PM PDT 24
Finished May 02 02:54:26 PM PDT 24
Peak memory 218588 kb
Host smart-71f55b31-6115-4caa-b9c9-6cb3b1287651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928721121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3928721121
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3732526171
Short name T398
Test name
Test status
Simulation time 115618251 ps
CPU time 1.19 seconds
Started May 02 02:52:31 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 206640 kb
Host smart-f3f10851-038d-45c4-aef9-f74d46e8a6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732526171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3732526171
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3793628696
Short name T137
Test name
Test status
Simulation time 32370882 ps
CPU time 0.8 seconds
Started May 02 02:52:31 PM PDT 24
Finished May 02 02:52:33 PM PDT 24
Peak memory 216024 kb
Host smart-3b7f4e2a-765f-47b2-b58d-6ee0bf34849d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793628696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3793628696
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3542897038
Short name T524
Test name
Test status
Simulation time 32852875 ps
CPU time 1.19 seconds
Started May 02 02:52:37 PM PDT 24
Finished May 02 02:52:39 PM PDT 24
Peak memory 219308 kb
Host smart-669fc3b3-fe15-4778-a858-e9f2846c7e8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542897038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3542897038
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2227411473
Short name T717
Test name
Test status
Simulation time 29386146 ps
CPU time 1.33 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 225484 kb
Host smart-a5dfd408-b84a-4c59-8de0-815ab6d0075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227411473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2227411473
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1199190247
Short name T289
Test name
Test status
Simulation time 139792619 ps
CPU time 1.56 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:35 PM PDT 24
Peak memory 218376 kb
Host smart-0c9d4881-26bc-42c7-b905-d34e26f1c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199190247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1199190247
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1262698606
Short name T319
Test name
Test status
Simulation time 22246343 ps
CPU time 1.06 seconds
Started May 02 02:52:37 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 215268 kb
Host smart-8d2dec24-d6b6-42be-92b8-12643cfc4a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262698606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1262698606
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2677863967
Short name T305
Test name
Test status
Simulation time 46102839 ps
CPU time 0.93 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:35 PM PDT 24
Peak memory 215108 kb
Host smart-e394b9e6-cb72-4018-8a9a-b0a2124a1b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677863967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2677863967
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3889455663
Short name T352
Test name
Test status
Simulation time 772432479 ps
CPU time 2.19 seconds
Started May 02 02:52:34 PM PDT 24
Finished May 02 02:52:38 PM PDT 24
Peak memory 219552 kb
Host smart-4e5b8238-f33b-433f-b050-1870d1281f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889455663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3889455663
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.78920705
Short name T207
Test name
Test status
Simulation time 357516076263 ps
CPU time 2103.9 seconds
Started May 02 02:52:35 PM PDT 24
Finished May 02 03:27:41 PM PDT 24
Peak memory 226000 kb
Host smart-53becfb0-7d6c-4df2-93a5-010fda2b0c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78920705 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.78920705
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2510588273
Short name T637
Test name
Test status
Simulation time 99614773 ps
CPU time 1.41 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:26 PM PDT 24
Peak memory 218520 kb
Host smart-bd51d001-c8cb-4c85-b49f-a5c82d55402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510588273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2510588273
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1244558612
Short name T439
Test name
Test status
Simulation time 213652539 ps
CPU time 1.17 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 217248 kb
Host smart-0dd1423d-8727-4c8c-a4a7-6a94198171a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244558612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1244558612
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3798016086
Short name T701
Test name
Test status
Simulation time 37923021 ps
CPU time 1.4 seconds
Started May 02 02:54:26 PM PDT 24
Finished May 02 02:54:29 PM PDT 24
Peak memory 216976 kb
Host smart-d7bf425f-ab9c-44a7-a196-5a393107c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798016086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3798016086
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3938281015
Short name T83
Test name
Test status
Simulation time 70231244 ps
CPU time 1.28 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 217872 kb
Host smart-72c04bbc-5ca8-4e85-a669-c00855a74aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938281015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3938281015
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3519229076
Short name T559
Test name
Test status
Simulation time 46433202 ps
CPU time 1.54 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:26 PM PDT 24
Peak memory 218232 kb
Host smart-ad36ad97-83fe-4a04-ae80-c3f60327d74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519229076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3519229076
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1991859209
Short name T313
Test name
Test status
Simulation time 150051780 ps
CPU time 1.01 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 216820 kb
Host smart-7baf3e93-8eca-4c51-8fb3-bfc6c6f43bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991859209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1991859209
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.58399850
Short name T90
Test name
Test status
Simulation time 56411009 ps
CPU time 1.36 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 216996 kb
Host smart-d5e11f16-4fc4-4293-af5c-1ff736ae417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58399850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.58399850
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2158831640
Short name T817
Test name
Test status
Simulation time 63256861 ps
CPU time 1.31 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 216968 kb
Host smart-9796426e-a1a7-4958-8b88-9fff9998b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158831640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2158831640
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4034071116
Short name T77
Test name
Test status
Simulation time 48833385 ps
CPU time 1.22 seconds
Started May 02 02:54:23 PM PDT 24
Finished May 02 02:54:25 PM PDT 24
Peak memory 218160 kb
Host smart-98a33655-0ec7-4eed-8302-db2b4e209934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034071116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4034071116
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2333995792
Short name T161
Test name
Test status
Simulation time 111728746 ps
CPU time 1.25 seconds
Started May 02 02:52:36 PM PDT 24
Finished May 02 02:52:38 PM PDT 24
Peak memory 215528 kb
Host smart-ed622d42-4bf3-41db-b7e5-0f86ab66d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333995792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2333995792
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2407308009
Short name T461
Test name
Test status
Simulation time 48164968 ps
CPU time 0.87 seconds
Started May 02 02:52:31 PM PDT 24
Finished May 02 02:52:33 PM PDT 24
Peak memory 206532 kb
Host smart-20fd1f2e-86c1-493d-b2b2-0085750e32d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407308009 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2407308009
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1228179928
Short name T129
Test name
Test status
Simulation time 21813178 ps
CPU time 0.88 seconds
Started May 02 02:52:37 PM PDT 24
Finished May 02 02:52:39 PM PDT 24
Peak memory 215228 kb
Host smart-32ca0541-11db-4dbe-b755-d46d4acec2b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228179928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1228179928
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.438805613
Short name T128
Test name
Test status
Simulation time 38097325 ps
CPU time 1.34 seconds
Started May 02 02:52:37 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 219420 kb
Host smart-bf607cde-7f6b-411d-a55b-60a34301543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438805613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.438805613
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3159322847
Short name T837
Test name
Test status
Simulation time 106788250 ps
CPU time 1.35 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:35 PM PDT 24
Peak memory 217128 kb
Host smart-79fee227-41c3-4414-a5ff-e6d2a3ea1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159322847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3159322847
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3845131386
Short name T4
Test name
Test status
Simulation time 52934886 ps
CPU time 0.95 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:36 PM PDT 24
Peak memory 223640 kb
Host smart-97cd6ecc-3a5e-4831-8f52-c0d40210d227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845131386 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3845131386
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1797824822
Short name T748
Test name
Test status
Simulation time 16398517 ps
CPU time 0.99 seconds
Started May 02 02:52:33 PM PDT 24
Finished May 02 02:52:36 PM PDT 24
Peak memory 215176 kb
Host smart-615ca54f-4a1e-4445-be40-7b68be2afbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797824822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1797824822
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.349672
Short name T730
Test name
Test status
Simulation time 780913571 ps
CPU time 4.75 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:39 PM PDT 24
Peak memory 216984 kb
Host smart-7bc47871-aaf1-44ff-9a8a-e34ee8d954a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.349672
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3011561906
Short name T211
Test name
Test status
Simulation time 144423956194 ps
CPU time 932.58 seconds
Started May 02 02:52:47 PM PDT 24
Finished May 02 03:08:21 PM PDT 24
Peak memory 221536 kb
Host smart-f3bd5cc0-d705-4f61-834d-56ddf8ee62e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011561906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3011561906
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3421012316
Short name T711
Test name
Test status
Simulation time 31127832 ps
CPU time 1.26 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 216840 kb
Host smart-c7e2ff22-a679-4c07-a2b0-b4b165eef41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421012316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3421012316
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3064581055
Short name T818
Test name
Test status
Simulation time 228712972 ps
CPU time 1.21 seconds
Started May 02 02:54:35 PM PDT 24
Finished May 02 02:54:37 PM PDT 24
Peak memory 219484 kb
Host smart-9c0cc2c7-12ec-4f0d-83ce-d78afdb23721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064581055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3064581055
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1341003320
Short name T566
Test name
Test status
Simulation time 63607220 ps
CPU time 1.5 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 216780 kb
Host smart-23c874d6-e1d4-4ace-b9ae-2547d365b416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341003320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1341003320
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3324194032
Short name T649
Test name
Test status
Simulation time 45214492 ps
CPU time 0.9 seconds
Started May 02 02:54:25 PM PDT 24
Finished May 02 02:54:28 PM PDT 24
Peak memory 216916 kb
Host smart-e7ee602f-0009-4aaf-8d90-a859c8ecc5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324194032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3324194032
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.615217737
Short name T283
Test name
Test status
Simulation time 48180993 ps
CPU time 1.63 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 218200 kb
Host smart-517b4f08-400e-4c33-b07f-49120bf90a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615217737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.615217737
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3652370099
Short name T344
Test name
Test status
Simulation time 310278927 ps
CPU time 2.42 seconds
Started May 02 02:54:26 PM PDT 24
Finished May 02 02:54:30 PM PDT 24
Peak memory 219536 kb
Host smart-f74d3d1c-5e9c-4d2c-b8b1-481ce5d7cf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652370099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3652370099
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.985095850
Short name T623
Test name
Test status
Simulation time 52922967 ps
CPU time 1.38 seconds
Started May 02 02:54:23 PM PDT 24
Finished May 02 02:54:26 PM PDT 24
Peak memory 218264 kb
Host smart-4ae23364-d947-4696-abd3-bf29ea79f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985095850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.985095850
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3104290606
Short name T536
Test name
Test status
Simulation time 103418912 ps
CPU time 1.24 seconds
Started May 02 02:54:23 PM PDT 24
Finished May 02 02:54:26 PM PDT 24
Peak memory 216836 kb
Host smart-c536e7d5-ca44-4573-aa6b-bbde92516557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104290606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3104290606
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3749371667
Short name T625
Test name
Test status
Simulation time 101904832 ps
CPU time 1.54 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 218144 kb
Host smart-245e1578-85f5-4038-a2ea-bba21ff49abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749371667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3749371667
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1422563067
Short name T343
Test name
Test status
Simulation time 126869291 ps
CPU time 1.54 seconds
Started May 02 02:54:24 PM PDT 24
Finished May 02 02:54:27 PM PDT 24
Peak memory 218404 kb
Host smart-58b220b4-6f51-4836-bb7c-c9510db69249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422563067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1422563067
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2905222319
Short name T421
Test name
Test status
Simulation time 29540420 ps
CPU time 1.25 seconds
Started May 02 02:52:38 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 215480 kb
Host smart-4b93d898-1b18-4af7-ad47-bee0f68c4d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905222319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2905222319
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.856412419
Short name T460
Test name
Test status
Simulation time 45632507 ps
CPU time 0.9 seconds
Started May 02 02:52:44 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 206544 kb
Host smart-5a282595-7a57-4a92-bba4-4325738ea35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856412419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.856412419
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1279184418
Short name T700
Test name
Test status
Simulation time 10934451 ps
CPU time 0.84 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 215908 kb
Host smart-3d25a40f-41c6-4453-b576-c42d05689ebf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279184418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1279184418
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.192843704
Short name T803
Test name
Test status
Simulation time 96247681 ps
CPU time 1.16 seconds
Started May 02 02:52:35 PM PDT 24
Finished May 02 02:52:38 PM PDT 24
Peak memory 215472 kb
Host smart-f438d5f3-6548-40e8-92db-1e8c04661834
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192843704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.192843704
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3246663072
Short name T793
Test name
Test status
Simulation time 31256590 ps
CPU time 0.83 seconds
Started May 02 02:52:32 PM PDT 24
Finished May 02 02:52:34 PM PDT 24
Peak memory 218432 kb
Host smart-90a185bb-a448-423a-b044-617a6105517e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246663072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3246663072
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2036945912
Short name T607
Test name
Test status
Simulation time 72065560 ps
CPU time 1.71 seconds
Started May 02 02:52:33 PM PDT 24
Finished May 02 02:52:36 PM PDT 24
Peak memory 218412 kb
Host smart-77981323-0a21-492f-b975-db72e7f2edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036945912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2036945912
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3949372483
Short name T51
Test name
Test status
Simulation time 27385812 ps
CPU time 1.09 seconds
Started May 02 02:52:36 PM PDT 24
Finished May 02 02:52:38 PM PDT 24
Peak memory 223932 kb
Host smart-ae335e81-9ca0-4871-b03c-45683c51c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949372483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3949372483
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2812576524
Short name T54
Test name
Test status
Simulation time 17187036 ps
CPU time 1.02 seconds
Started May 02 02:52:35 PM PDT 24
Finished May 02 02:52:37 PM PDT 24
Peak memory 215068 kb
Host smart-70031377-325f-449b-b2e5-dabacb5413ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812576524 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2812576524
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3490347350
Short name T349
Test name
Test status
Simulation time 68379343 ps
CPU time 1.91 seconds
Started May 02 02:52:37 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 216836 kb
Host smart-c4d8115e-d91a-4b92-89b7-435643d5065e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490347350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3490347350
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1023121295
Short name T436
Test name
Test status
Simulation time 71389240569 ps
CPU time 498.17 seconds
Started May 02 02:52:36 PM PDT 24
Finished May 02 03:00:56 PM PDT 24
Peak memory 218160 kb
Host smart-0d0de2f1-6fb7-4600-9762-634903b34514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023121295 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1023121295
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.176487556
Short name T612
Test name
Test status
Simulation time 80400592 ps
CPU time 1.6 seconds
Started May 02 02:54:29 PM PDT 24
Finished May 02 02:54:32 PM PDT 24
Peak memory 218044 kb
Host smart-ba81f0ed-390c-4c81-883d-c0a84ced681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176487556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.176487556
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.200581478
Short name T809
Test name
Test status
Simulation time 72260680 ps
CPU time 2.5 seconds
Started May 02 02:54:28 PM PDT 24
Finished May 02 02:54:31 PM PDT 24
Peak memory 218196 kb
Host smart-eda2e3a4-1c9c-4fcc-b23d-a91d46fd9705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200581478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.200581478
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.768532459
Short name T838
Test name
Test status
Simulation time 57990166 ps
CPU time 1.24 seconds
Started May 02 02:54:31 PM PDT 24
Finished May 02 02:54:34 PM PDT 24
Peak memory 218488 kb
Host smart-046f89a4-0b1f-4b95-902e-cb70ae8c31a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768532459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.768532459
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3682584268
Short name T610
Test name
Test status
Simulation time 62095348 ps
CPU time 1.49 seconds
Started May 02 02:54:33 PM PDT 24
Finished May 02 02:54:36 PM PDT 24
Peak memory 218220 kb
Host smart-b84a69f3-47e3-4aae-8da6-d88109599620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682584268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3682584268
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3596581741
Short name T606
Test name
Test status
Simulation time 81156352 ps
CPU time 1.19 seconds
Started May 02 02:54:32 PM PDT 24
Finished May 02 02:54:34 PM PDT 24
Peak memory 215156 kb
Host smart-e15ac60a-ac98-4342-9941-7e07978865dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596581741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3596581741
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3381354901
Short name T433
Test name
Test status
Simulation time 95382930 ps
CPU time 1.11 seconds
Started May 02 02:54:33 PM PDT 24
Finished May 02 02:54:35 PM PDT 24
Peak memory 216908 kb
Host smart-31aabec8-b5ea-4510-8160-504034b7f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381354901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3381354901
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.990444313
Short name T212
Test name
Test status
Simulation time 57035064 ps
CPU time 1.27 seconds
Started May 02 02:54:29 PM PDT 24
Finished May 02 02:54:31 PM PDT 24
Peak memory 217000 kb
Host smart-2ef0e421-e2d0-4600-8182-6b35718ec34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990444313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.990444313
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.600349770
Short name T816
Test name
Test status
Simulation time 41274495 ps
CPU time 1.18 seconds
Started May 02 02:54:32 PM PDT 24
Finished May 02 02:54:34 PM PDT 24
Peak memory 216904 kb
Host smart-5f2d1b75-86a8-455e-af22-6d2b2d840c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600349770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.600349770
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1233978831
Short name T658
Test name
Test status
Simulation time 83858905 ps
CPU time 1.15 seconds
Started May 02 02:54:31 PM PDT 24
Finished May 02 02:54:33 PM PDT 24
Peak memory 219376 kb
Host smart-33492588-d18c-4e58-8394-ffbc8acc886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233978831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1233978831
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.596181273
Short name T779
Test name
Test status
Simulation time 49312536 ps
CPU time 1.83 seconds
Started May 02 02:54:33 PM PDT 24
Finished May 02 02:54:36 PM PDT 24
Peak memory 218052 kb
Host smart-8c8ecfce-3674-40b0-a99a-16c64dafc68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596181273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.596181273
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3093976573
Short name T798
Test name
Test status
Simulation time 202406650 ps
CPU time 1.42 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:36 PM PDT 24
Peak memory 215572 kb
Host smart-8e2358c7-8242-4239-8f03-8506ca679c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093976573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3093976573
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2807252857
Short name T544
Test name
Test status
Simulation time 15143819 ps
CPU time 0.91 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:33 PM PDT 24
Peak memory 206476 kb
Host smart-5d9ee497-e289-420b-82ec-153681806afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807252857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2807252857
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.542829134
Short name T143
Test name
Test status
Simulation time 38245928 ps
CPU time 0.9 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:36 PM PDT 24
Peak memory 215992 kb
Host smart-fff858d0-98df-46b5-a4aa-061195ea5151
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542829134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.542829134
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.949892378
Short name T122
Test name
Test status
Simulation time 122259306 ps
CPU time 1.28 seconds
Started May 02 02:51:35 PM PDT 24
Finished May 02 02:51:38 PM PDT 24
Peak memory 216776 kb
Host smart-cb505ec0-f4cc-478c-8d58-4f32a4870005
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949892378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.949892378
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.41466285
Short name T116
Test name
Test status
Simulation time 49278698 ps
CPU time 0.97 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:36 PM PDT 24
Peak memory 220424 kb
Host smart-8ed7876e-51c1-401e-af7a-ef6f0305c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41466285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.41466285
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3748164931
Short name T761
Test name
Test status
Simulation time 49138796 ps
CPU time 1.25 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 218980 kb
Host smart-a729332f-04b2-44df-926e-e75e46f4be1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748164931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3748164931
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3690726706
Short name T168
Test name
Test status
Simulation time 36204181 ps
CPU time 0.86 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 215564 kb
Host smart-fdcc5c51-74d6-4d3c-92fc-9dc63dcbcadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690726706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3690726706
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2293892303
Short name T259
Test name
Test status
Simulation time 74827598 ps
CPU time 0.88 seconds
Started May 02 02:51:31 PM PDT 24
Finished May 02 02:51:33 PM PDT 24
Peak memory 206980 kb
Host smart-22b1a6d1-fc14-4867-a37b-d347a7b3ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293892303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2293892303
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1460924602
Short name T15
Test name
Test status
Simulation time 479541895 ps
CPU time 4.35 seconds
Started May 02 02:51:31 PM PDT 24
Finished May 02 02:51:37 PM PDT 24
Peak memory 237400 kb
Host smart-eb06314d-567d-455b-911e-9b29dfc45ac0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460924602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1460924602
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.51447564
Short name T653
Test name
Test status
Simulation time 17336459 ps
CPU time 1.04 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:36 PM PDT 24
Peak memory 215164 kb
Host smart-864405c9-33a7-4b64-9954-2cb93f21b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51447564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.51447564
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.377214490
Short name T371
Test name
Test status
Simulation time 204641091 ps
CPU time 4.37 seconds
Started May 02 02:51:34 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 216964 kb
Host smart-40bb5c7c-edd8-412c-bd81-d48d22e22143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377214490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.377214490
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1726570644
Short name T198
Test name
Test status
Simulation time 96330236960 ps
CPU time 275.75 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:56:10 PM PDT 24
Peak memory 217564 kb
Host smart-4fd4b82b-18a6-4ef8-8d75-a308f4cc5f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726570644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1726570644
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3253258594
Short name T130
Test name
Test status
Simulation time 112726244 ps
CPU time 1.17 seconds
Started May 02 02:52:38 PM PDT 24
Finished May 02 02:52:40 PM PDT 24
Peak memory 215552 kb
Host smart-bac73ab5-fb50-4909-bc8b-5725915f276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253258594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3253258594
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4158301540
Short name T598
Test name
Test status
Simulation time 61859483 ps
CPU time 0.95 seconds
Started May 02 02:52:42 PM PDT 24
Finished May 02 02:52:44 PM PDT 24
Peak memory 215112 kb
Host smart-b57947b0-049b-47a2-a277-3681858e1c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158301540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4158301540
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1417764400
Short name T403
Test name
Test status
Simulation time 37440465 ps
CPU time 0.9 seconds
Started May 02 02:52:43 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 215192 kb
Host smart-dc3bff35-24e4-4f96-9263-6d95d19c3251
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417764400 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1417764400
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.151806882
Short name T474
Test name
Test status
Simulation time 18932843 ps
CPU time 1.1 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:42 PM PDT 24
Peak memory 223884 kb
Host smart-30610824-a1a9-40ea-b9c9-b98aa1f839dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151806882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.151806882
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.433297410
Short name T599
Test name
Test status
Simulation time 60577171 ps
CPU time 1.32 seconds
Started May 02 02:52:43 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 219404 kb
Host smart-c65ba4f2-a7fc-41f3-9af3-27ceb6f897b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433297410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.433297410
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.2231886410
Short name T202
Test name
Test status
Simulation time 19202336 ps
CPU time 1.02 seconds
Started May 02 02:52:40 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 215160 kb
Host smart-2d06d7c1-5c39-4205-9269-e485fa1ccf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231886410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2231886410
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2570753287
Short name T835
Test name
Test status
Simulation time 755061757 ps
CPU time 5.5 seconds
Started May 02 02:52:40 PM PDT 24
Finished May 02 02:52:47 PM PDT 24
Peak memory 216980 kb
Host smart-f8a038ab-0cb1-4fc9-9331-c42e4582872b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570753287 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2570753287
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3575608614
Short name T472
Test name
Test status
Simulation time 258807385077 ps
CPU time 1702.38 seconds
Started May 02 02:52:40 PM PDT 24
Finished May 02 03:21:04 PM PDT 24
Peak memory 227136 kb
Host smart-1d907b91-2dc8-4e3a-9541-ce2acdac0e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575608614 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3575608614
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.662146812
Short name T266
Test name
Test status
Simulation time 30520878 ps
CPU time 1.27 seconds
Started May 02 02:52:41 PM PDT 24
Finished May 02 02:52:44 PM PDT 24
Peak memory 215544 kb
Host smart-bd13964f-ecdf-4bd4-9032-5f70b72e0db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662146812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.662146812
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3971823548
Short name T328
Test name
Test status
Simulation time 28623009 ps
CPU time 0.96 seconds
Started May 02 02:52:43 PM PDT 24
Finished May 02 02:52:45 PM PDT 24
Peak memory 206484 kb
Host smart-bbccc227-67ce-4969-98f6-1a46436bab05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971823548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3971823548
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3599088274
Short name T669
Test name
Test status
Simulation time 12142611 ps
CPU time 0.89 seconds
Started May 02 02:52:44 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 216220 kb
Host smart-3cd55498-72a5-4b8d-b322-cb3d8a8f2ea3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599088274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3599088274
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1473461664
Short name T106
Test name
Test status
Simulation time 95203404 ps
CPU time 1.14 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:41 PM PDT 24
Peak memory 216588 kb
Host smart-f737ce88-c377-4bfa-ad33-68d38d8232a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473461664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1473461664
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4084956166
Short name T445
Test name
Test status
Simulation time 17613829 ps
CPU time 1.03 seconds
Started May 02 02:52:41 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 217912 kb
Host smart-e3fdafcd-c16a-4397-a1b5-980b1d3052bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084956166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4084956166
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1667779729
Short name T516
Test name
Test status
Simulation time 308063359 ps
CPU time 4.41 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:46 PM PDT 24
Peak memory 217124 kb
Host smart-4494446e-e736-497e-854a-18f47157aac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667779729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1667779729
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.3476497574
Short name T591
Test name
Test status
Simulation time 20866469 ps
CPU time 0.92 seconds
Started May 02 02:52:40 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 215112 kb
Host smart-3e13c89c-45f7-4d10-8237-e6489153c0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476497574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3476497574
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1203599382
Short name T533
Test name
Test status
Simulation time 231628315 ps
CPU time 4.31 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:45 PM PDT 24
Peak memory 216820 kb
Host smart-0ed83cd3-01d2-4807-b2cb-7b785b496ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203599382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1203599382
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3090455460
Short name T498
Test name
Test status
Simulation time 77276243298 ps
CPU time 710.02 seconds
Started May 02 02:52:40 PM PDT 24
Finished May 02 03:04:32 PM PDT 24
Peak memory 220344 kb
Host smart-2ea311e8-a83a-45f8-b19a-20332d2421df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090455460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3090455460
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3068934971
Short name T422
Test name
Test status
Simulation time 93706734 ps
CPU time 1.29 seconds
Started May 02 02:52:52 PM PDT 24
Finished May 02 02:52:55 PM PDT 24
Peak memory 215508 kb
Host smart-e947a46a-3c58-4880-8069-0232c9938679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068934971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3068934971
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2944821941
Short name T774
Test name
Test status
Simulation time 19029638 ps
CPU time 0.98 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:53 PM PDT 24
Peak memory 206512 kb
Host smart-9e3800fc-c105-4620-96b3-f48ec181e8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944821941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2944821941
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1867323256
Short name T712
Test name
Test status
Simulation time 10101966 ps
CPU time 0.88 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:52 PM PDT 24
Peak memory 215684 kb
Host smart-778bf868-ddc5-4d24-984d-2b75ef14c52a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867323256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1867323256
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2549624366
Short name T600
Test name
Test status
Simulation time 34196556 ps
CPU time 0.99 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:53 PM PDT 24
Peak memory 219388 kb
Host smart-0842eed9-177b-4551-ac68-af21a6e72616
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549624366 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2549624366
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3769292463
Short name T511
Test name
Test status
Simulation time 99792445 ps
CPU time 1.18 seconds
Started May 02 02:52:49 PM PDT 24
Finished May 02 02:52:51 PM PDT 24
Peak memory 219380 kb
Host smart-cf423f40-e4e7-4d46-85a7-ce18821fcb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769292463 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3769292463
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.741929977
Short name T294
Test name
Test status
Simulation time 77104223 ps
CPU time 1.38 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:41 PM PDT 24
Peak memory 218232 kb
Host smart-af6f9bed-57d8-448a-b975-7c3acf6e6d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741929977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.741929977
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3369172457
Short name T454
Test name
Test status
Simulation time 23321304 ps
CPU time 1.07 seconds
Started May 02 02:52:39 PM PDT 24
Finished May 02 02:52:43 PM PDT 24
Peak memory 215784 kb
Host smart-ddb8c6e6-695a-4d1e-bff6-a7e91597f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369172457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3369172457
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2342528831
Short name T351
Test name
Test status
Simulation time 15640145 ps
CPU time 1 seconds
Started May 02 02:52:41 PM PDT 24
Finished May 02 02:52:44 PM PDT 24
Peak memory 215136 kb
Host smart-903abc39-608f-4c68-bfaf-b324a2e97ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342528831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2342528831
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3002488694
Short name T478
Test name
Test status
Simulation time 158011618 ps
CPU time 3.72 seconds
Started May 02 02:52:43 PM PDT 24
Finished May 02 02:52:49 PM PDT 24
Peak memory 216768 kb
Host smart-280e5aec-68ea-48a4-b888-afc97b867418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002488694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3002488694
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2586970955
Short name T661
Test name
Test status
Simulation time 89295017838 ps
CPU time 1165.45 seconds
Started May 02 02:52:44 PM PDT 24
Finished May 02 03:12:11 PM PDT 24
Peak memory 224064 kb
Host smart-0d4bbee1-5bfe-4b63-997b-c0d4e91f8730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586970955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2586970955
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2633666645
Short name T163
Test name
Test status
Simulation time 102879970 ps
CPU time 1.12 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:52 PM PDT 24
Peak memory 215540 kb
Host smart-2eb7da4a-43ec-48a4-870f-11c9aa438f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633666645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2633666645
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4129526793
Short name T840
Test name
Test status
Simulation time 39286926 ps
CPU time 1.26 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:58 PM PDT 24
Peak memory 214864 kb
Host smart-f5b7a0e4-fe57-492d-95c4-40ecea6ce2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129526793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4129526793
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.106848092
Short name T193
Test name
Test status
Simulation time 48127274 ps
CPU time 0.88 seconds
Started May 02 02:52:48 PM PDT 24
Finished May 02 02:52:50 PM PDT 24
Peak memory 215256 kb
Host smart-5dd7b405-8223-4d44-9ea8-c7cb5a3417fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106848092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.106848092
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.3628703684
Short name T471
Test name
Test status
Simulation time 62690028 ps
CPU time 0.95 seconds
Started May 02 02:52:53 PM PDT 24
Finished May 02 02:52:56 PM PDT 24
Peak memory 218536 kb
Host smart-168816ae-bcbd-4278-a903-fda9d2952c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628703684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3628703684
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_intr.1972636682
Short name T466
Test name
Test status
Simulation time 32645616 ps
CPU time 0.83 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:52 PM PDT 24
Peak memory 215180 kb
Host smart-8c09c2c6-0fd0-4c1f-8aef-0422ad9d071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972636682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1972636682
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1568825817
Short name T629
Test name
Test status
Simulation time 26661079 ps
CPU time 0.92 seconds
Started May 02 02:52:48 PM PDT 24
Finished May 02 02:52:50 PM PDT 24
Peak memory 215152 kb
Host smart-4e71d874-7f5e-4e6f-a9c8-cca885b34419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568825817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1568825817
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.52632389
Short name T509
Test name
Test status
Simulation time 721665227 ps
CPU time 4.17 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:56 PM PDT 24
Peak memory 215096 kb
Host smart-fab41f4f-f7b3-4116-873d-8429cdfcdae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52632389 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.52632389
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.190554062
Short name T594
Test name
Test status
Simulation time 26652648943 ps
CPU time 300.83 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:57:53 PM PDT 24
Peak memory 223504 kb
Host smart-648aea74-8419-430e-b5d6-fd4f65ae6d94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190554062 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.190554062
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2528951158
Short name T413
Test name
Test status
Simulation time 88620368 ps
CPU time 1.23 seconds
Started May 02 02:52:48 PM PDT 24
Finished May 02 02:52:50 PM PDT 24
Peak memory 215540 kb
Host smart-bcd9e475-e820-4b9f-bd24-4b9552ce21eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528951158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2528951158
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1843168430
Short name T484
Test name
Test status
Simulation time 52953981 ps
CPU time 0.91 seconds
Started May 02 02:52:52 PM PDT 24
Finished May 02 02:52:55 PM PDT 24
Peak memory 214756 kb
Host smart-2c58901d-2bdd-4720-8fd6-a4e2fd49030c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843168430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1843168430
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.586460938
Short name T142
Test name
Test status
Simulation time 30548604 ps
CPU time 0.8 seconds
Started May 02 02:52:52 PM PDT 24
Finished May 02 02:52:55 PM PDT 24
Peak memory 216044 kb
Host smart-33d89c47-de2e-49d1-85e5-1be4cb0c8b75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586460938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.586460938
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2065487882
Short name T586
Test name
Test status
Simulation time 66304371 ps
CPU time 1.26 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:58 PM PDT 24
Peak memory 216576 kb
Host smart-d728649a-9ae5-4c6a-a0b0-ba9f365a9651
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065487882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2065487882
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1017195905
Short name T1
Test name
Test status
Simulation time 34613098 ps
CPU time 0.89 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:58 PM PDT 24
Peak memory 217764 kb
Host smart-ac6807cd-3eb1-4043-b174-6821959491e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017195905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1017195905
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.1810131784
Short name T152
Test name
Test status
Simulation time 26255539 ps
CPU time 0.93 seconds
Started May 02 02:52:49 PM PDT 24
Finished May 02 02:52:51 PM PDT 24
Peak memory 215400 kb
Host smart-7c5a5489-1338-49e1-bc60-1b19d27d17f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810131784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1810131784
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1729891924
Short name T364
Test name
Test status
Simulation time 25183933 ps
CPU time 0.99 seconds
Started May 02 02:52:54 PM PDT 24
Finished May 02 02:52:57 PM PDT 24
Peak memory 215128 kb
Host smart-1ce78123-4fc9-4351-97ef-1fb2e7a991c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729891924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1729891924
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2214485264
Short name T827
Test name
Test status
Simulation time 90533276 ps
CPU time 1.45 seconds
Started May 02 02:52:48 PM PDT 24
Finished May 02 02:52:50 PM PDT 24
Peak memory 206976 kb
Host smart-e769f468-16ac-44c1-96e1-768263e230b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214485264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2214485264
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1514865933
Short name T195
Test name
Test status
Simulation time 139253224448 ps
CPU time 1809.32 seconds
Started May 02 02:52:53 PM PDT 24
Finished May 02 03:23:04 PM PDT 24
Peak memory 227824 kb
Host smart-c68c3692-d021-4275-82a3-eb7b970101bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514865933 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1514865933
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.758412980
Short name T383
Test name
Test status
Simulation time 14006963 ps
CPU time 0.94 seconds
Started May 02 02:53:01 PM PDT 24
Finished May 02 02:53:03 PM PDT 24
Peak memory 206440 kb
Host smart-e0802be7-75a2-4208-aef0-6a5d8ec4ecf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758412980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.758412980
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.767432463
Short name T426
Test name
Test status
Simulation time 39699271 ps
CPU time 0.78 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 216068 kb
Host smart-9e826a54-0f93-47f4-a3a6-26d716c11bd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767432463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.767432463
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2724894789
Short name T690
Test name
Test status
Simulation time 30225826 ps
CPU time 1.25 seconds
Started May 02 02:53:00 PM PDT 24
Finished May 02 02:53:03 PM PDT 24
Peak memory 216708 kb
Host smart-54e09c6f-07fe-4b59-81fd-2109b4cf2dad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724894789 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2724894789
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.233374412
Short name T605
Test name
Test status
Simulation time 97703046 ps
CPU time 1.12 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:53 PM PDT 24
Peak memory 219700 kb
Host smart-44de2224-1da2-4e34-8df1-90f00b7b3026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233374412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.233374412
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.959530851
Short name T765
Test name
Test status
Simulation time 46838294 ps
CPU time 1.22 seconds
Started May 02 02:52:52 PM PDT 24
Finished May 02 02:52:56 PM PDT 24
Peak memory 218464 kb
Host smart-eacf3a60-f3c8-445c-a8f3-5b654ef66fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959530851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.959530851
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3898835627
Short name T467
Test name
Test status
Simulation time 19879581 ps
CPU time 1.07 seconds
Started May 02 02:52:52 PM PDT 24
Finished May 02 02:52:55 PM PDT 24
Peak memory 215764 kb
Host smart-50c02baa-b208-435f-a1ee-1500780a6439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898835627 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3898835627
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3874862012
Short name T834
Test name
Test status
Simulation time 46986417 ps
CPU time 0.9 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:53 PM PDT 24
Peak memory 215136 kb
Host smart-f04088d6-f609-4ce0-95e8-4231bb3138ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874862012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3874862012
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.898713300
Short name T676
Test name
Test status
Simulation time 26887296 ps
CPU time 1.21 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 02:52:53 PM PDT 24
Peak memory 215140 kb
Host smart-3768a7f8-503a-4c20-abdc-a1f5272108d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898713300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.898713300
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3079060215
Short name T369
Test name
Test status
Simulation time 45201118283 ps
CPU time 951.31 seconds
Started May 02 02:52:50 PM PDT 24
Finished May 02 03:08:43 PM PDT 24
Peak memory 218236 kb
Host smart-047e11a7-47d9-4f97-ae70-f65108a9f385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079060215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3079060215
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3807488504
Short name T258
Test name
Test status
Simulation time 36111947 ps
CPU time 1.23 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:53:00 PM PDT 24
Peak memory 215288 kb
Host smart-65d0089e-0c88-481a-9701-a2bd171a439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807488504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3807488504
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4221614207
Short name T321
Test name
Test status
Simulation time 40692782 ps
CPU time 0.87 seconds
Started May 02 02:52:54 PM PDT 24
Finished May 02 02:52:57 PM PDT 24
Peak memory 214696 kb
Host smart-78b45b1a-fd8a-48de-962b-65614f4397ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221614207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4221614207
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3025865005
Short name T725
Test name
Test status
Simulation time 14323981 ps
CPU time 0.95 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:05 PM PDT 24
Peak memory 216396 kb
Host smart-93828ba7-46b9-438b-899d-23a9dd244b77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025865005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3025865005
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.54050055
Short name T105
Test name
Test status
Simulation time 53842854 ps
CPU time 1.13 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 216804 kb
Host smart-32c8dc96-0abc-4e85-af8d-c80df6b9280a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54050055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_dis
able_auto_req_mode.54050055
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1326965111
Short name T812
Test name
Test status
Simulation time 72725848 ps
CPU time 1.07 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 219348 kb
Host smart-58c75aad-186b-4321-aed6-dcf2e5579ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326965111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1326965111
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.701748099
Short name T729
Test name
Test status
Simulation time 42931741 ps
CPU time 1.18 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 218260 kb
Host smart-50231f21-4d41-49fb-bb78-9e55d6d61a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701748099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.701748099
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3942546645
Short name T333
Test name
Test status
Simulation time 22715868 ps
CPU time 1.15 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215252 kb
Host smart-33137f7e-e0ee-474d-bb44-9d0096e3b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942546645 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3942546645
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2512601164
Short name T683
Test name
Test status
Simulation time 52566086 ps
CPU time 0.93 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215168 kb
Host smart-3d154ed4-94f1-48c8-9d67-465fa9282e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512601164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2512601164
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2433365063
Short name T664
Test name
Test status
Simulation time 296254901 ps
CPU time 3.51 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 218024 kb
Host smart-ff7edfb3-268d-463f-b2d0-93d50acfc547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433365063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2433365063
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2419806561
Short name T36
Test name
Test status
Simulation time 621247932184 ps
CPU time 907.87 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 03:08:06 PM PDT 24
Peak memory 222500 kb
Host smart-9c0d7f6e-f4cb-412e-8698-2a6905e60d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419806561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2419806561
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.1763154720
Short name T807
Test name
Test status
Simulation time 16182603 ps
CPU time 0.89 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 206544 kb
Host smart-7f003575-c640-48d8-8dad-ad428b5eaf12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763154720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1763154720
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3720996455
Short name T718
Test name
Test status
Simulation time 12691440 ps
CPU time 0.89 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 216064 kb
Host smart-23a2d399-b3a3-4f7a-a5c2-f8930ac304d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720996455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3720996455
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1066634178
Short name T756
Test name
Test status
Simulation time 71611616 ps
CPU time 1.2 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 216804 kb
Host smart-3ef13919-7d54-4c26-a251-a9c6c5891b80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066634178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1066634178
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3334755045
Short name T184
Test name
Test status
Simulation time 116158345 ps
CPU time 0.91 seconds
Started May 02 02:53:00 PM PDT 24
Finished May 02 02:53:02 PM PDT 24
Peak memory 218320 kb
Host smart-562570b6-74d1-4541-be2a-7de68d26442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334755045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3334755045
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3526881292
Short name T583
Test name
Test status
Simulation time 41188002 ps
CPU time 1.57 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 216812 kb
Host smart-5a360d96-bcdd-49ca-be6e-8e6a7d4f8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526881292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3526881292
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3547859971
Short name T821
Test name
Test status
Simulation time 27096401 ps
CPU time 0.96 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:00 PM PDT 24
Peak memory 215700 kb
Host smart-637c617b-ff1c-4290-a69a-3b2fdddf8e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547859971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3547859971
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3908851504
Short name T797
Test name
Test status
Simulation time 18787418 ps
CPU time 1.01 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215172 kb
Host smart-3bbba2cc-fcdf-477a-bd27-29d3f8ea4923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908851504 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3908851504
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1307356845
Short name T553
Test name
Test status
Simulation time 326983065 ps
CPU time 1.15 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 215192 kb
Host smart-877ba9ca-d815-4fec-a612-513570c4fccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307356845 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1307356845
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2283965167
Short name T787
Test name
Test status
Simulation time 372147845495 ps
CPU time 2132.13 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 03:28:33 PM PDT 24
Peak memory 225856 kb
Host smart-2a9edd4c-b034-486d-88ed-22374bdd0fe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283965167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2283965167
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.93411463
Short name T91
Test name
Test status
Simulation time 76472438 ps
CPU time 1.27 seconds
Started May 02 02:52:55 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 215548 kb
Host smart-efa8705f-3cab-4cd8-81fa-dbc28865a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93411463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.93411463
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1229531000
Short name T582
Test name
Test status
Simulation time 17337176 ps
CPU time 0.97 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:00 PM PDT 24
Peak memory 215112 kb
Host smart-dcc2a7d0-c03d-49d2-a263-a9949be952f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229531000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1229531000
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2550002966
Short name T479
Test name
Test status
Simulation time 20980789 ps
CPU time 0.89 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:05 PM PDT 24
Peak memory 216080 kb
Host smart-8bc47ee3-12cc-4488-92f8-b8b03370f82a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550002966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2550002966
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3963395990
Short name T177
Test name
Test status
Simulation time 49840451 ps
CPU time 1.08 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 216804 kb
Host smart-1e783c24-99a9-4a8a-8a73-4560198d475b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963395990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3963395990
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.867638231
Short name T639
Test name
Test status
Simulation time 32587420 ps
CPU time 1.04 seconds
Started May 02 02:53:01 PM PDT 24
Finished May 02 02:53:03 PM PDT 24
Peak memory 218556 kb
Host smart-4da99ed0-2ba6-4750-b58d-c04ab5f952d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867638231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.867638231
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1472532702
Short name T420
Test name
Test status
Simulation time 90910376 ps
CPU time 1.34 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:00 PM PDT 24
Peak memory 218284 kb
Host smart-ed80b24e-d821-49ce-9ee3-96bc54c6955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472532702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1472532702
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1926042148
Short name T496
Test name
Test status
Simulation time 24751036 ps
CPU time 0.96 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:52:59 PM PDT 24
Peak memory 215288 kb
Host smart-1721c683-8b3e-452f-9fbd-a40cc220d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926042148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1926042148
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1199597634
Short name T628
Test name
Test status
Simulation time 23503967 ps
CPU time 0.95 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:02 PM PDT 24
Peak memory 215140 kb
Host smart-f55bf843-22e1-428a-a4bf-9767beac0fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199597634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1199597634
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3403042905
Short name T310
Test name
Test status
Simulation time 556649496 ps
CPU time 5.31 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:04 PM PDT 24
Peak memory 216792 kb
Host smart-0efd51a4-d2dc-4e46-a46b-4bc623b44abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403042905 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3403042905
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3924832444
Short name T631
Test name
Test status
Simulation time 454520390097 ps
CPU time 2926.52 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 03:41:45 PM PDT 24
Peak memory 234008 kb
Host smart-09dd57a0-3220-4f57-88bf-426462f9e2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924832444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3924832444
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3394322286
Short name T162
Test name
Test status
Simulation time 65527722 ps
CPU time 1.19 seconds
Started May 02 02:53:04 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 215520 kb
Host smart-bf1c8938-bb71-40f5-94c2-ed267b8f106c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394322286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3394322286
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.216288995
Short name T587
Test name
Test status
Simulation time 19920458 ps
CPU time 0.83 seconds
Started May 02 02:53:05 PM PDT 24
Finished May 02 02:53:07 PM PDT 24
Peak memory 206744 kb
Host smart-8a90b78b-3663-4f2b-a0a8-1c336858ccaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216288995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.216288995
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.229192057
Short name T126
Test name
Test status
Simulation time 16342421 ps
CPU time 0.83 seconds
Started May 02 02:53:08 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 215264 kb
Host smart-bc5f04bd-4e20-476c-b1a1-df64aafaa68e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229192057 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.229192057
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3096752989
Short name T503
Test name
Test status
Simulation time 83145268 ps
CPU time 1.01 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 218132 kb
Host smart-0ba109d8-f937-4d1f-8d32-e6471accd3b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096752989 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3096752989
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.4152730715
Short name T435
Test name
Test status
Simulation time 83858961 ps
CPU time 0.98 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:53:04 PM PDT 24
Peak memory 223636 kb
Host smart-5f31438d-6819-46ff-9968-7c1c573f7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152730715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.4152730715
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.722903386
Short name T749
Test name
Test status
Simulation time 99352289 ps
CPU time 1.41 seconds
Started May 02 02:52:54 PM PDT 24
Finished May 02 02:52:57 PM PDT 24
Peak memory 218648 kb
Host smart-391b6d76-c358-4911-a6b2-c1f5e6330dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722903386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.722903386
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2614711170
Short name T744
Test name
Test status
Simulation time 22709872 ps
CPU time 1.13 seconds
Started May 02 02:52:58 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215292 kb
Host smart-b25ccf36-fd76-4107-b8b9-f885f1698463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614711170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2614711170
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4070440935
Short name T72
Test name
Test status
Simulation time 27645590 ps
CPU time 0.96 seconds
Started May 02 02:52:57 PM PDT 24
Finished May 02 02:53:01 PM PDT 24
Peak memory 215160 kb
Host smart-521d65d7-b70b-425c-87ff-8168b0bd1032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070440935 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4070440935
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2715581503
Short name T826
Test name
Test status
Simulation time 300308713 ps
CPU time 6.09 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 215204 kb
Host smart-142526b5-6f19-48bc-b22f-c567b79d4ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715581503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2715581503
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.344808658
Short name T287
Test name
Test status
Simulation time 61766786804 ps
CPU time 359.38 seconds
Started May 02 02:52:56 PM PDT 24
Finished May 02 02:58:58 PM PDT 24
Peak memory 218196 kb
Host smart-aa1784df-4a20-4bda-a1c5-617e089ea942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344808658 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.344808658
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1469297202
Short name T268
Test name
Test status
Simulation time 73176363 ps
CPU time 1.24 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 02:51:35 PM PDT 24
Peak memory 215536 kb
Host smart-18062280-2450-4187-945a-75adc27ef6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469297202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1469297202
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2272426622
Short name T330
Test name
Test status
Simulation time 17000793 ps
CPU time 0.87 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:51:41 PM PDT 24
Peak memory 206564 kb
Host smart-3bf61c56-1535-4ee8-94f3-bdd1d008ee11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272426622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2272426622
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4193507762
Short name T179
Test name
Test status
Simulation time 22640899 ps
CPU time 0.9 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 02:51:42 PM PDT 24
Peak memory 216040 kb
Host smart-d3d3c9f5-f74a-4081-9e8b-41df8ddc7a41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193507762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4193507762
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3772693560
Short name T784
Test name
Test status
Simulation time 32310135 ps
CPU time 1.25 seconds
Started May 02 02:51:43 PM PDT 24
Finished May 02 02:51:45 PM PDT 24
Peak memory 216604 kb
Host smart-fa92f832-c7de-4d2f-840d-cd2558efbbf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772693560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3772693560
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.664411126
Short name T505
Test name
Test status
Simulation time 28473883 ps
CPU time 1.41 seconds
Started May 02 02:51:43 PM PDT 24
Finished May 02 02:51:45 PM PDT 24
Peak memory 225320 kb
Host smart-ed1c358b-403a-453a-8088-d873e1294b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664411126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.664411126
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2784721144
Short name T336
Test name
Test status
Simulation time 294198620 ps
CPU time 1.2 seconds
Started May 02 02:51:32 PM PDT 24
Finished May 02 02:51:34 PM PDT 24
Peak memory 217028 kb
Host smart-be98c05b-61e7-4377-bec1-8042565378cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784721144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2784721144
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4034762910
Short name T50
Test name
Test status
Simulation time 20813876 ps
CPU time 1.07 seconds
Started May 02 02:51:31 PM PDT 24
Finished May 02 02:51:33 PM PDT 24
Peak memory 215288 kb
Host smart-b5de96ce-6755-48f4-90c4-e710073f5c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034762910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4034762910
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1499982477
Short name T264
Test name
Test status
Simulation time 18419937 ps
CPU time 1.05 seconds
Started May 02 02:51:35 PM PDT 24
Finished May 02 02:51:38 PM PDT 24
Peak memory 206932 kb
Host smart-60c3966b-6c62-49e6-ad7f-fe07be4e2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499982477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1499982477
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3159745905
Short name T55
Test name
Test status
Simulation time 1752206519 ps
CPU time 8.21 seconds
Started May 02 02:51:41 PM PDT 24
Finished May 02 02:51:51 PM PDT 24
Peak memory 237908 kb
Host smart-2e95fc34-96d7-4dff-af76-0b9508e808d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159745905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3159745905
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1760762747
Short name T592
Test name
Test status
Simulation time 15026357 ps
CPU time 1.01 seconds
Started May 02 02:51:34 PM PDT 24
Finished May 02 02:51:36 PM PDT 24
Peak memory 215144 kb
Host smart-fe407f5b-d117-4158-83df-57efa8fa8db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760762747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1760762747
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2576339234
Short name T339
Test name
Test status
Simulation time 280553063 ps
CPU time 5.29 seconds
Started May 02 02:51:34 PM PDT 24
Finished May 02 02:51:41 PM PDT 24
Peak memory 215232 kb
Host smart-7164907f-3223-4683-af93-717c98c2ca01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576339234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2576339234
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1168581085
Short name T397
Test name
Test status
Simulation time 139065262342 ps
CPU time 632.09 seconds
Started May 02 02:51:33 PM PDT 24
Finished May 02 03:02:07 PM PDT 24
Peak memory 220688 kb
Host smart-ab527880-10b9-48fe-a68c-7e748468bf54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168581085 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1168581085
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2967275039
Short name T269
Test name
Test status
Simulation time 42045652 ps
CPU time 1.15 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:53:04 PM PDT 24
Peak memory 215484 kb
Host smart-69dab53b-f1aa-41a0-b9ae-39287245093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967275039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2967275039
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1983207742
Short name T395
Test name
Test status
Simulation time 31616548 ps
CPU time 0.77 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 206776 kb
Host smart-eba5323b-7e3a-41f9-8128-57569d7c089e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983207742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1983207742
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2323571099
Short name T778
Test name
Test status
Simulation time 17855635 ps
CPU time 0.82 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 215272 kb
Host smart-586dceec-cb42-486b-924f-3b1aae204fb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323571099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2323571099
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1954291045
Short name T627
Test name
Test status
Simulation time 136188362 ps
CPU time 1.11 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 216752 kb
Host smart-4441a349-f021-43cb-8467-e1ef85a8b515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954291045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1954291045
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.840154614
Short name T151
Test name
Test status
Simulation time 22921507 ps
CPU time 0.94 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:05 PM PDT 24
Peak memory 218076 kb
Host smart-33c9f8c2-20f2-42f8-aa73-34031895121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840154614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.840154614
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3122378041
Short name T292
Test name
Test status
Simulation time 118933558 ps
CPU time 1.22 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:05 PM PDT 24
Peak memory 216888 kb
Host smart-79c327e4-1aa2-4544-876c-070339503e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122378041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3122378041
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2109597077
Short name T215
Test name
Test status
Simulation time 50524202 ps
CPU time 0.9 seconds
Started May 02 02:53:04 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 215120 kb
Host smart-4450ddad-8885-464b-85af-b31e6222e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109597077 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2109597077
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2814596718
Short name T626
Test name
Test status
Simulation time 24753870 ps
CPU time 0.96 seconds
Started May 02 02:53:04 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 215144 kb
Host smart-e3fe43f2-c388-4b28-b288-449d0587ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814596718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2814596718
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3747077261
Short name T379
Test name
Test status
Simulation time 501149862 ps
CPU time 3.19 seconds
Started May 02 02:53:06 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 217040 kb
Host smart-57e5793a-79c0-4134-bad4-7aa73bef67ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747077261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3747077261
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1008242769
Short name T384
Test name
Test status
Simulation time 1161335158653 ps
CPU time 3480.5 seconds
Started May 02 02:53:06 PM PDT 24
Finished May 02 03:51:07 PM PDT 24
Peak memory 232040 kb
Host smart-e9666ca0-e622-4057-aa3f-6f9b6a260f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008242769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1008242769
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.893310210
Short name T680
Test name
Test status
Simulation time 46034717 ps
CPU time 1.25 seconds
Started May 02 02:53:04 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 215500 kb
Host smart-4f1c8acb-037c-4d70-862f-199742866fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893310210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.893310210
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1964542071
Short name T641
Test name
Test status
Simulation time 26080774 ps
CPU time 0.92 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:53:04 PM PDT 24
Peak memory 214756 kb
Host smart-1436f09c-2a8a-4707-b0a8-53afcc26a385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964542071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1964542071
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2136582131
Short name T190
Test name
Test status
Simulation time 17166687 ps
CPU time 0.82 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 215216 kb
Host smart-8c9ded32-cc4b-445c-a269-dada16b5578c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136582131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2136582131
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.226087479
Short name T108
Test name
Test status
Simulation time 26139353 ps
CPU time 1.01 seconds
Started May 02 02:53:08 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 219288 kb
Host smart-f46a2eaa-0e13-4442-adac-8ebafa1c48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226087479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.226087479
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3615132400
Short name T570
Test name
Test status
Simulation time 82738182 ps
CPU time 1.39 seconds
Started May 02 02:53:08 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 218180 kb
Host smart-f96bfa89-aff7-4cce-bc7f-729e78ae934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615132400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3615132400
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1626248395
Short name T831
Test name
Test status
Simulation time 40473627 ps
CPU time 0.98 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 215324 kb
Host smart-04680b37-244a-460f-bbbf-a3d927b52331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626248395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1626248395
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3752581471
Short name T548
Test name
Test status
Simulation time 19608167 ps
CPU time 1.02 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 02:53:09 PM PDT 24
Peak memory 215132 kb
Host smart-c259e121-f2e6-4a3c-bce2-0f0c85945c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752581471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3752581471
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3020794585
Short name T742
Test name
Test status
Simulation time 708167473 ps
CPU time 4.78 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:53:08 PM PDT 24
Peak memory 215256 kb
Host smart-d501d595-c0a9-4dc5-bc5c-b544aa84f7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020794585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3020794585
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.609056452
Short name T723
Test name
Test status
Simulation time 42259017048 ps
CPU time 1097.83 seconds
Started May 02 02:53:05 PM PDT 24
Finished May 02 03:11:24 PM PDT 24
Peak memory 220940 kb
Host smart-82ba4912-3486-4c28-ab7e-3e471e7afb2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609056452 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.609056452
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.1187439917
Short name T825
Test name
Test status
Simulation time 23873224 ps
CPU time 0.88 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:11 PM PDT 24
Peak memory 206472 kb
Host smart-46755cc8-201b-43a9-907e-398429c7a637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187439917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1187439917
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.76449933
Short name T60
Test name
Test status
Simulation time 30723238 ps
CPU time 0.9 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 216064 kb
Host smart-5e269e58-243f-49a3-ab62-abd0806df6ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76449933 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.76449933
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3221355547
Short name T3
Test name
Test status
Simulation time 46130491 ps
CPU time 1.38 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 216700 kb
Host smart-759af92d-f116-40ad-a691-9c595519ac91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221355547 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3221355547
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1177560370
Short name T181
Test name
Test status
Simulation time 96515204 ps
CPU time 1.12 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 219528 kb
Host smart-8a7733d4-1beb-4a70-bcbf-7a64987cc28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177560370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1177560370
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1613021622
Short name T160
Test name
Test status
Simulation time 45461628 ps
CPU time 1.6 seconds
Started May 02 02:53:03 PM PDT 24
Finished May 02 02:53:05 PM PDT 24
Peak memory 218080 kb
Host smart-4884b85d-fee7-4c9f-a2f7-37ad49617686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613021622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1613021622
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.2236334978
Short name T836
Test name
Test status
Simulation time 43555009 ps
CPU time 0.9 seconds
Started May 02 02:53:04 PM PDT 24
Finished May 02 02:53:06 PM PDT 24
Peak memory 215164 kb
Host smart-45b17c66-6631-44b4-8345-22caf0b1a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236334978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2236334978
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2735604559
Short name T458
Test name
Test status
Simulation time 771727910 ps
CPU time 5.3 seconds
Started May 02 02:53:08 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 215256 kb
Host smart-50848901-69ff-4b0a-b393-1065fe187eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735604559 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2735604559
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.672880559
Short name T58
Test name
Test status
Simulation time 42273272466 ps
CPU time 219.02 seconds
Started May 02 02:53:02 PM PDT 24
Finished May 02 02:56:42 PM PDT 24
Peak memory 223616 kb
Host smart-45470ec0-2255-4875-8a65-43fcf45be785
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672880559 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.672880559
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1400106439
Short name T262
Test name
Test status
Simulation time 85828571 ps
CPU time 1.15 seconds
Started May 02 02:53:10 PM PDT 24
Finished May 02 02:53:13 PM PDT 24
Peak memory 215548 kb
Host smart-f18dd4b9-05f7-4e32-8792-c868f058ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400106439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1400106439
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3503541606
Short name T353
Test name
Test status
Simulation time 14897845 ps
CPU time 0.89 seconds
Started May 02 02:53:21 PM PDT 24
Finished May 02 02:53:22 PM PDT 24
Peak memory 206520 kb
Host smart-ff046046-3659-4a9f-b1a2-69eb9185a472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503541606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3503541606
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.68609314
Short name T191
Test name
Test status
Simulation time 41151904 ps
CPU time 0.84 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:10 PM PDT 24
Peak memory 216044 kb
Host smart-f5d4236a-5121-4e1f-9ede-257921041fd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68609314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.68609314
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3111632270
Short name T117
Test name
Test status
Simulation time 53806932 ps
CPU time 1.09 seconds
Started May 02 02:53:21 PM PDT 24
Finished May 02 02:53:23 PM PDT 24
Peak memory 216808 kb
Host smart-8def0140-c6cd-4ad3-a0b2-4dd9c0a0ca56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111632270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3111632270
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3377963624
Short name T104
Test name
Test status
Simulation time 25002107 ps
CPU time 1.01 seconds
Started May 02 02:53:13 PM PDT 24
Finished May 02 02:53:16 PM PDT 24
Peak memory 219348 kb
Host smart-5b9cf6ea-bbd3-402a-bee4-1402227de807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377963624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3377963624
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2181276756
Short name T476
Test name
Test status
Simulation time 87188611 ps
CPU time 1.94 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:15 PM PDT 24
Peak memory 219712 kb
Host smart-7df7831c-ca55-45b6-8647-e28af0badc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181276756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2181276756
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3464122859
Short name T558
Test name
Test status
Simulation time 24562812 ps
CPU time 0.92 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:12 PM PDT 24
Peak memory 215364 kb
Host smart-7876495c-c311-4ecf-837d-87d912b15264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464122859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3464122859
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3563531303
Short name T155
Test name
Test status
Simulation time 14974878 ps
CPU time 1 seconds
Started May 02 02:53:08 PM PDT 24
Finished May 02 02:53:11 PM PDT 24
Peak memory 215132 kb
Host smart-e62e02b9-c448-4d71-aa49-aaf63e0db4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563531303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3563531303
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2968754812
Short name T574
Test name
Test status
Simulation time 242650101 ps
CPU time 4.9 seconds
Started May 02 02:53:15 PM PDT 24
Finished May 02 02:53:21 PM PDT 24
Peak memory 220052 kb
Host smart-08c23205-fcd6-48c5-acc9-45e613b0a0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968754812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2968754812
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.300186047
Short name T643
Test name
Test status
Simulation time 53290108822 ps
CPU time 1426.39 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 03:17:00 PM PDT 24
Peak memory 223688 kb
Host smart-0398ed15-5636-49ad-9600-7d52e25cec5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300186047 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.300186047
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2016783916
Short name T25
Test name
Test status
Simulation time 196802231 ps
CPU time 1.2 seconds
Started May 02 02:53:09 PM PDT 24
Finished May 02 02:53:11 PM PDT 24
Peak memory 215572 kb
Host smart-95ccf003-ba05-4ffd-947c-754007cf40ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016783916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2016783916
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2379522215
Short name T528
Test name
Test status
Simulation time 31270354 ps
CPU time 0.99 seconds
Started May 02 02:53:13 PM PDT 24
Finished May 02 02:53:15 PM PDT 24
Peak memory 206520 kb
Host smart-ac3270a5-3990-400d-9673-ba3db14e85d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379522215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2379522215
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1444255198
Short name T648
Test name
Test status
Simulation time 69316767 ps
CPU time 0.79 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 215748 kb
Host smart-1f7c6c9b-9d80-4f5e-a7c9-9069991225c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444255198 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1444255198
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4110029660
Short name T839
Test name
Test status
Simulation time 38931439 ps
CPU time 1.23 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 219368 kb
Host smart-47453616-c136-4cf9-be10-82bc85c3ca6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110029660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4110029660
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3671260585
Short name T172
Test name
Test status
Simulation time 66525352 ps
CPU time 0.93 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 218428 kb
Host smart-8bd6f3c2-a3d5-4a0b-94dd-dbd7290dcf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671260585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3671260585
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2790409740
Short name T358
Test name
Test status
Simulation time 85640367 ps
CPU time 2.01 seconds
Started May 02 02:53:15 PM PDT 24
Finished May 02 02:53:18 PM PDT 24
Peak memory 217092 kb
Host smart-0733bee3-aada-4326-a776-3758d06cab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790409740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2790409740
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3798978366
Short name T497
Test name
Test status
Simulation time 37933436 ps
CPU time 0.92 seconds
Started May 02 02:53:22 PM PDT 24
Finished May 02 02:53:24 PM PDT 24
Peak memory 215292 kb
Host smart-0342d220-760a-42fb-b0a1-fb88b7d4ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798978366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3798978366
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.185156440
Short name T452
Test name
Test status
Simulation time 19838806 ps
CPU time 1.02 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 215168 kb
Host smart-fdbc5464-e28d-4c58-bff3-cd5b6eebeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185156440 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.185156440
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1978978118
Short name T707
Test name
Test status
Simulation time 776268171 ps
CPU time 4.37 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:18 PM PDT 24
Peak memory 216744 kb
Host smart-675e7dd3-19bc-42d5-856b-8688c194ce41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978978118 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1978978118
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3509558115
Short name T196
Test name
Test status
Simulation time 110055698000 ps
CPU time 1223.95 seconds
Started May 02 02:53:07 PM PDT 24
Finished May 02 03:13:33 PM PDT 24
Peak memory 221868 kb
Host smart-51cc8387-3f8e-4d9b-a8f1-94dac152813b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509558115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3509558115
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.48837265
Short name T462
Test name
Test status
Simulation time 188580004 ps
CPU time 1.35 seconds
Started May 02 02:53:11 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 215536 kb
Host smart-f755ceb0-3eef-452b-9da0-3e6b9930f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48837265 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.48837265
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.18396016
Short name T312
Test name
Test status
Simulation time 52066496 ps
CPU time 0.95 seconds
Started May 02 02:53:10 PM PDT 24
Finished May 02 02:53:13 PM PDT 24
Peak memory 206532 kb
Host smart-a731a12c-6804-4d2a-9917-c99888952f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18396016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.18396016
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.4184423257
Short name T324
Test name
Test status
Simulation time 37718969 ps
CPU time 1.32 seconds
Started May 02 02:53:10 PM PDT 24
Finished May 02 02:53:13 PM PDT 24
Peak memory 216788 kb
Host smart-f1bf1fa7-5753-4dd5-b9a6-fac52ca1f457
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184423257 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.4184423257
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1488259066
Short name T590
Test name
Test status
Simulation time 19644453 ps
CPU time 1.08 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 218424 kb
Host smart-4aedbcf3-aace-49da-a66f-ec4426422c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488259066 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1488259066
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2912477116
Short name T584
Test name
Test status
Simulation time 41143566 ps
CPU time 1.61 seconds
Started May 02 02:53:13 PM PDT 24
Finished May 02 02:53:16 PM PDT 24
Peak memory 217936 kb
Host smart-da4d0e5f-46e2-4585-91f2-ecc426f669e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912477116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2912477116
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.247329497
Short name T27
Test name
Test status
Simulation time 28742177 ps
CPU time 0.85 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 02:53:14 PM PDT 24
Peak memory 215488 kb
Host smart-ecf6264f-3006-4870-994d-3800ca53f6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247329497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.247329497
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3610671842
Short name T490
Test name
Test status
Simulation time 22171948 ps
CPU time 0.95 seconds
Started May 02 02:53:13 PM PDT 24
Finished May 02 02:53:16 PM PDT 24
Peak memory 215224 kb
Host smart-c2cd18fc-d52e-46eb-93be-c9817e2d73c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610671842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3610671842
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.653394415
Short name T646
Test name
Test status
Simulation time 204774004 ps
CPU time 4.56 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 216748 kb
Host smart-7d1aaf55-2711-4046-be2d-5fbbaa410688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653394415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.653394415
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1050504454
Short name T209
Test name
Test status
Simulation time 267190486167 ps
CPU time 1096.67 seconds
Started May 02 02:53:12 PM PDT 24
Finished May 02 03:11:30 PM PDT 24
Peak memory 221028 kb
Host smart-82ba03d6-80c9-4646-a861-10dc89695aaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050504454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1050504454
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.4253899589
Short name T131
Test name
Test status
Simulation time 25815597 ps
CPU time 1.16 seconds
Started May 02 02:53:25 PM PDT 24
Finished May 02 02:53:28 PM PDT 24
Peak memory 215592 kb
Host smart-29beb545-cabe-45da-9026-da6d8617c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253899589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4253899589
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1018885512
Short name T390
Test name
Test status
Simulation time 16762045 ps
CPU time 0.97 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 215084 kb
Host smart-66856d9c-5470-4c58-b872-4f35a2734be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018885512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1018885512
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2865080345
Short name T491
Test name
Test status
Simulation time 18608699 ps
CPU time 0.83 seconds
Started May 02 02:53:20 PM PDT 24
Finished May 02 02:53:22 PM PDT 24
Peak memory 215976 kb
Host smart-3dd57bcd-373c-468a-bcf5-866e93dbf76f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865080345 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2865080345
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2461551657
Short name T107
Test name
Test status
Simulation time 59675970 ps
CPU time 1.15 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 216592 kb
Host smart-6478cdcb-bd3e-4f60-83b1-4ce517184cd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461551657 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2461551657
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3919569974
Short name T473
Test name
Test status
Simulation time 20232660 ps
CPU time 1.18 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 223816 kb
Host smart-1bcd83e5-72b1-4d9d-954d-fb0cd4aa11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919569974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3919569974
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2640170219
Short name T12
Test name
Test status
Simulation time 154160149 ps
CPU time 1.21 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 219708 kb
Host smart-851d2140-72d7-410d-9892-3c7d896b473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640170219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2640170219
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1356753678
Short name T99
Test name
Test status
Simulation time 24229722 ps
CPU time 0.91 seconds
Started May 02 02:53:21 PM PDT 24
Finished May 02 02:53:22 PM PDT 24
Peak memory 215732 kb
Host smart-840755bb-135c-4a2a-b338-beac44ea9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356753678 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1356753678
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2044636944
Short name T419
Test name
Test status
Simulation time 84570012 ps
CPU time 0.92 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 215188 kb
Host smart-a82e971c-b8b1-4745-ab50-2e00bebb0266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044636944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2044636944
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1533154256
Short name T49
Test name
Test status
Simulation time 125553807 ps
CPU time 2.76 seconds
Started May 02 02:53:27 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 216984 kb
Host smart-d17fe237-5671-4818-91b5-f343b0fb7f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533154256 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1533154256
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3147256700
Short name T679
Test name
Test status
Simulation time 100858053322 ps
CPU time 738.43 seconds
Started May 02 02:53:22 PM PDT 24
Finished May 02 03:05:42 PM PDT 24
Peak memory 219984 kb
Host smart-fd235a35-2c8a-4f84-bd17-4290d522f8bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147256700 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3147256700
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2949442874
Short name T132
Test name
Test status
Simulation time 71508853 ps
CPU time 1.13 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 215496 kb
Host smart-e538840b-71b8-45ac-b9ee-5bf4f7e18d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949442874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2949442874
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4104919077
Short name T68
Test name
Test status
Simulation time 146726293 ps
CPU time 0.93 seconds
Started May 02 02:53:25 PM PDT 24
Finished May 02 02:53:28 PM PDT 24
Peak memory 215072 kb
Host smart-2bc62dc4-0022-4708-a04d-eba7d5a43c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104919077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4104919077
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3578495749
Short name T169
Test name
Test status
Simulation time 14907903 ps
CPU time 0.86 seconds
Started May 02 02:53:20 PM PDT 24
Finished May 02 02:53:22 PM PDT 24
Peak memory 215216 kb
Host smart-4bc25dc2-1fcf-4958-8847-d84763ee9a13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578495749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3578495749
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1415822234
Short name T121
Test name
Test status
Simulation time 46941811 ps
CPU time 1.57 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 216600 kb
Host smart-5d17cf43-714a-4586-9514-6931427415b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415822234 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1415822234
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1576451269
Short name T670
Test name
Test status
Simulation time 20669439 ps
CPU time 1.08 seconds
Started May 02 02:53:22 PM PDT 24
Finished May 02 02:53:23 PM PDT 24
Peak memory 218404 kb
Host smart-ca9a1d97-4ec8-4861-872b-5996fa4e2150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576451269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1576451269
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3599473786
Short name T415
Test name
Test status
Simulation time 85024451 ps
CPU time 1.12 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:27 PM PDT 24
Peak memory 216904 kb
Host smart-7d7469fc-6bc0-4ebd-a762-e4d582d31624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599473786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3599473786
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2433238240
Short name T810
Test name
Test status
Simulation time 21194688 ps
CPU time 1.15 seconds
Started May 02 02:53:25 PM PDT 24
Finished May 02 02:53:28 PM PDT 24
Peak memory 215468 kb
Host smart-7aed4693-bdec-4fa9-aa60-ede3db2c9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433238240 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2433238240
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4224492617
Short name T401
Test name
Test status
Simulation time 16378468 ps
CPU time 0.97 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 215144 kb
Host smart-086cab52-241d-497d-bff4-897e8d62d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224492617 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4224492617
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3215974098
Short name T695
Test name
Test status
Simulation time 243168485 ps
CPU time 1.91 seconds
Started May 02 02:53:25 PM PDT 24
Finished May 02 02:53:29 PM PDT 24
Peak memory 215200 kb
Host smart-da49d431-c472-4d4d-afd1-775289a99a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215974098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3215974098
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2106217755
Short name T601
Test name
Test status
Simulation time 146268291052 ps
CPU time 876.59 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 03:08:04 PM PDT 24
Peak memory 220352 kb
Host smart-fcc0e0ed-80f8-4dbe-8682-3364f92bf2df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106217755 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2106217755
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2726293579
Short name T253
Test name
Test status
Simulation time 132914786 ps
CPU time 1.25 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 215552 kb
Host smart-31404fa9-a54a-478c-8645-b5e458ce743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726293579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2726293579
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2107121865
Short name T796
Test name
Test status
Simulation time 38477962 ps
CPU time 0.8 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 206296 kb
Host smart-9b9999b5-1c20-4f29-ac00-871eff1bec1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107121865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2107121865
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1593407498
Short name T630
Test name
Test status
Simulation time 12745271 ps
CPU time 0.85 seconds
Started May 02 02:53:22 PM PDT 24
Finished May 02 02:53:24 PM PDT 24
Peak memory 215392 kb
Host smart-2ddcff69-0e7d-4e1a-bf17-dc5bbbadf299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593407498 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1593407498
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1754947211
Short name T560
Test name
Test status
Simulation time 82844992 ps
CPU time 1.04 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 216556 kb
Host smart-2b9764ad-1621-489a-8433-03afcef71810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754947211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1754947211
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3526846070
Short name T342
Test name
Test status
Simulation time 43171045 ps
CPU time 1.13 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 219640 kb
Host smart-4723b4c5-37ce-48e6-abf0-85943a541261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526846070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3526846070
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1990042316
Short name T768
Test name
Test status
Simulation time 124827194 ps
CPU time 1.71 seconds
Started May 02 02:53:22 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 219844 kb
Host smart-332a09bd-cf31-4af5-a804-2e9facec809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990042316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1990042316
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1666237748
Short name T451
Test name
Test status
Simulation time 42669964 ps
CPU time 0.91 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:24 PM PDT 24
Peak memory 215348 kb
Host smart-683e66eb-d78a-447b-bade-9f0e6e0908d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666237748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1666237748
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2720125132
Short name T504
Test name
Test status
Simulation time 42041106 ps
CPU time 0.94 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:25 PM PDT 24
Peak memory 206980 kb
Host smart-0e9cae04-e58f-40aa-b6d9-9ddf87ede4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720125132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2720125132
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4202952017
Short name T405
Test name
Test status
Simulation time 617418871 ps
CPU time 3.72 seconds
Started May 02 02:53:27 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 216872 kb
Host smart-622dabde-1079-4efa-b4d3-bf76c9764317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202952017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4202952017
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1920838273
Short name T724
Test name
Test status
Simulation time 85648141971 ps
CPU time 509.04 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 03:01:55 PM PDT 24
Peak memory 219220 kb
Host smart-d8ed2ffd-a5ee-41e8-be81-f06c8ce83a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920838273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1920838273
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3908169524
Short name T423
Test name
Test status
Simulation time 364514881 ps
CPU time 1.5 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 215536 kb
Host smart-1e5e7bce-29b7-4ffe-85cc-1a05e6e1f351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908169524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3908169524
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3687814576
Short name T506
Test name
Test status
Simulation time 37912632 ps
CPU time 1.05 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:27 PM PDT 24
Peak memory 214864 kb
Host smart-de13660a-e205-4a9e-90ea-4d2ac89ba912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687814576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3687814576
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3350255854
Short name T556
Test name
Test status
Simulation time 20692562 ps
CPU time 0.86 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 215216 kb
Host smart-2835b3b5-3936-45c2-8d9a-70ab721f9059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350255854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3350255854
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3409331364
Short name T785
Test name
Test status
Simulation time 60342210 ps
CPU time 1.11 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 02:53:29 PM PDT 24
Peak memory 216524 kb
Host smart-a2e1e904-8bf1-4a3f-992c-54f052fc87ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409331364 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3409331364
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2840389154
Short name T64
Test name
Test status
Simulation time 84791952 ps
CPU time 0.85 seconds
Started May 02 02:53:25 PM PDT 24
Finished May 02 02:53:28 PM PDT 24
Peak memory 218292 kb
Host smart-a03131c5-ed64-4f5e-8eb9-ccd0b5c9d5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840389154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2840389154
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1865733212
Short name T350
Test name
Test status
Simulation time 125312290 ps
CPU time 2.65 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 219820 kb
Host smart-54460d08-33fb-4836-8a78-07b701ea62fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865733212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1865733212
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2976263925
Short name T492
Test name
Test status
Simulation time 25555615 ps
CPU time 0.9 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 215384 kb
Host smart-04a38f43-d447-41b4-bae3-55951c54772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976263925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2976263925
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1415900243
Short name T71
Test name
Test status
Simulation time 14668234 ps
CPU time 0.96 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 215160 kb
Host smart-2fca3d91-37f3-4ab5-96fe-9e3f6d0afd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415900243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1415900243
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2428666457
Short name T624
Test name
Test status
Simulation time 770144507 ps
CPU time 4.76 seconds
Started May 02 02:53:28 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 216988 kb
Host smart-8f71adb0-5dbd-4a50-ade9-44c506c3bab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428666457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2428666457
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2317761416
Short name T199
Test name
Test status
Simulation time 19230191834 ps
CPU time 335.38 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 02:59:03 PM PDT 24
Peak memory 223168 kb
Host smart-5e3dbfff-8ded-4198-b34f-d6dc7684a89e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317761416 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2317761416
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4073322064
Short name T150
Test name
Test status
Simulation time 30728585 ps
CPU time 1.25 seconds
Started May 02 02:51:38 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 215564 kb
Host smart-f7254f8c-bb98-4bab-a847-d6b42edf47f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073322064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4073322064
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1023925686
Short name T769
Test name
Test status
Simulation time 229707831 ps
CPU time 0.91 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:51:41 PM PDT 24
Peak memory 215032 kb
Host smart-e67073a2-f4ee-4a9f-9a70-b64787e93f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023925686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1023925686
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2622104059
Short name T543
Test name
Test status
Simulation time 46367528 ps
CPU time 1.01 seconds
Started May 02 02:51:42 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 219464 kb
Host smart-070f5a7d-c850-4ff7-95fc-b58a17115af7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622104059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2622104059
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1234153183
Short name T526
Test name
Test status
Simulation time 26836589 ps
CPU time 0.94 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 218656 kb
Host smart-88a70b0b-b5f4-4a63-b2c0-901d4fcb0584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234153183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1234153183
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2185040330
Short name T446
Test name
Test status
Simulation time 54153629 ps
CPU time 1.47 seconds
Started May 02 02:51:41 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 219648 kb
Host smart-048bcb17-3d2d-4b4e-b045-fe865312e8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185040330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2185040330
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.646956846
Short name T557
Test name
Test status
Simulation time 27951120 ps
CPU time 1 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 215196 kb
Host smart-cb7bd316-ecf4-4462-ab8c-d93d7efee480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646956846 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.646956846
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2358350293
Short name T23
Test name
Test status
Simulation time 75596542 ps
CPU time 0.92 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 206960 kb
Host smart-c1bcdf3a-f351-461a-bc77-27c00e61a394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358350293 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2358350293
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3054821419
Short name T792
Test name
Test status
Simulation time 21082486 ps
CPU time 0.93 seconds
Started May 02 02:51:41 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 215136 kb
Host smart-e1b03100-cb8d-4044-9bb6-2201d36dfb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054821419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3054821419
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.311836367
Short name T740
Test name
Test status
Simulation time 190533964 ps
CPU time 4.21 seconds
Started May 02 02:51:38 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 216764 kb
Host smart-4307f039-e0d2-4247-9510-24cbec4ffd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311836367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.311836367
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_err.4014162330
Short name T112
Test name
Test status
Simulation time 23657296 ps
CPU time 1.15 seconds
Started May 02 02:53:27 PM PDT 24
Finished May 02 02:53:29 PM PDT 24
Peak memory 218212 kb
Host smart-6986ff0d-1416-4b7a-8daa-b266de317c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014162330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4014162330
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3104587059
Short name T362
Test name
Test status
Simulation time 43631270 ps
CPU time 1.45 seconds
Started May 02 02:53:27 PM PDT 24
Finished May 02 02:53:30 PM PDT 24
Peak memory 217908 kb
Host smart-136918f0-7dd1-4cdc-8530-e8b78a16dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104587059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3104587059
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3755510844
Short name T412
Test name
Test status
Simulation time 60706515 ps
CPU time 1.2 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:27 PM PDT 24
Peak memory 225404 kb
Host smart-44b6e14f-7318-4eb9-a597-8770890c129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755510844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3755510844
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1228767077
Short name T396
Test name
Test status
Simulation time 31972697 ps
CPU time 1.28 seconds
Started May 02 02:53:28 PM PDT 24
Finished May 02 02:53:30 PM PDT 24
Peak memory 217908 kb
Host smart-b22b3c95-54f1-436b-b093-ace40a2ffaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228767077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1228767077
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2571735261
Short name T115
Test name
Test status
Simulation time 27523625 ps
CPU time 1.31 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 02:53:29 PM PDT 24
Peak memory 229592 kb
Host smart-f5f2b5e9-6972-4a0c-8cb2-b4589535d789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571735261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2571735261
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3489079270
Short name T354
Test name
Test status
Simulation time 45882466 ps
CPU time 1.35 seconds
Started May 02 02:53:23 PM PDT 24
Finished May 02 02:53:26 PM PDT 24
Peak memory 216816 kb
Host smart-d719929c-5e94-4b5d-b34a-41a55c6af1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489079270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3489079270
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.318888295
Short name T682
Test name
Test status
Simulation time 34265917 ps
CPU time 1.07 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 218348 kb
Host smart-854189f9-b07c-40bb-8eda-eaa9bb39ed40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318888295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.318888295
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3882343132
Short name T551
Test name
Test status
Simulation time 315082585 ps
CPU time 1.59 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 219604 kb
Host smart-8b7ab7ad-7e70-418f-8b33-70d4a98bd161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882343132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3882343132
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.10843119
Short name T710
Test name
Test status
Simulation time 31984962 ps
CPU time 1.16 seconds
Started May 02 02:53:24 PM PDT 24
Finished May 02 02:53:27 PM PDT 24
Peak memory 223904 kb
Host smart-267379a0-f9a9-4bf5-b215-72f93f13bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10843119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.10843119
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2669093407
Short name T273
Test name
Test status
Simulation time 41892265 ps
CPU time 1.52 seconds
Started May 02 02:53:26 PM PDT 24
Finished May 02 02:53:29 PM PDT 24
Peak memory 218100 kb
Host smart-eed76d69-e0fd-463c-bd3e-98db48125f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669093407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2669093407
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3210371500
Short name T6
Test name
Test status
Simulation time 38572451 ps
CPU time 1.24 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 228424 kb
Host smart-bf460acb-c605-419e-90b0-3375511fc5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210371500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3210371500
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3318714719
Short name T545
Test name
Test status
Simulation time 88806420 ps
CPU time 1.46 seconds
Started May 02 02:53:28 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 218388 kb
Host smart-90aa0549-3e0c-4b70-9bf9-44e85bcb97a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318714719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3318714719
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.741500361
Short name T457
Test name
Test status
Simulation time 18059779 ps
CPU time 1.11 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 218224 kb
Host smart-1ae0397a-f914-4ba8-a50f-7b948bae0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741500361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.741500361
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3965683805
Short name T487
Test name
Test status
Simulation time 83021791 ps
CPU time 1.2 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 219504 kb
Host smart-e305c13e-2148-49e6-8571-14fdcc15f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965683805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3965683805
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2892506386
Short name T135
Test name
Test status
Simulation time 33836071 ps
CPU time 0.84 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:31 PM PDT 24
Peak memory 218144 kb
Host smart-60e750ff-c5b7-4f48-a04d-4688ab93fbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892506386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2892506386
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3422936716
Short name T488
Test name
Test status
Simulation time 46281786 ps
CPU time 1.5 seconds
Started May 02 02:53:29 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 218036 kb
Host smart-fdadbb3a-c59d-4a17-a25e-248efec6eeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422936716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3422936716
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1872155169
Short name T145
Test name
Test status
Simulation time 20096796 ps
CPU time 1.17 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 223876 kb
Host smart-b54160af-9b09-4894-8dc5-a8f407a88c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872155169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1872155169
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.4064674160
Short name T96
Test name
Test status
Simulation time 58993408 ps
CPU time 1.38 seconds
Started May 02 02:53:30 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 219544 kb
Host smart-2f1a94b5-ab68-4d21-8021-10c40c00c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064674160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.4064674160
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.4274410426
Short name T603
Test name
Test status
Simulation time 19391006 ps
CPU time 1.04 seconds
Started May 02 02:53:30 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 218120 kb
Host smart-bdc6216a-57ba-4c89-9404-bc03dd9a976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274410426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4274410426
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.664046241
Short name T363
Test name
Test status
Simulation time 41285424 ps
CPU time 1.08 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 217020 kb
Host smart-36bfaad6-8705-402d-ae85-99ab5398832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664046241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.664046241
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.331616804
Short name T247
Test name
Test status
Simulation time 24290080 ps
CPU time 1.23 seconds
Started May 02 02:51:38 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 215556 kb
Host smart-eea4ad4c-1323-4531-a81c-caf39701f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331616804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.331616804
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1845324780
Short name T685
Test name
Test status
Simulation time 34750224 ps
CPU time 0.87 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 02:51:42 PM PDT 24
Peak memory 206392 kb
Host smart-e6f83b82-37ea-47fc-ac64-67a1064ef863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845324780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1845324780
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3859490719
Short name T173
Test name
Test status
Simulation time 21744864 ps
CPU time 0.83 seconds
Started May 02 02:51:41 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 216140 kb
Host smart-970db9a1-60c9-4ea2-af4d-3e08618edbfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859490719 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3859490719
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.1913537236
Short name T355
Test name
Test status
Simulation time 19391705 ps
CPU time 1.07 seconds
Started May 02 02:51:41 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 218136 kb
Host smart-8b28b5ec-5467-4d91-85c5-acbd729d8fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913537236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1913537236
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.47568785
Short name T78
Test name
Test status
Simulation time 76219543 ps
CPU time 1.27 seconds
Started May 02 02:51:39 PM PDT 24
Finished May 02 02:51:42 PM PDT 24
Peak memory 218216 kb
Host smart-b1a40c78-88b3-485d-a4a8-a97aa76a2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47568785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.47568785
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3214217084
Short name T31
Test name
Test status
Simulation time 24653929 ps
CPU time 0.97 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 02:51:43 PM PDT 24
Peak memory 215696 kb
Host smart-1dff93fb-a398-4437-9420-69d2612388cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214217084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3214217084
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2242662238
Short name T260
Test name
Test status
Simulation time 29320967 ps
CPU time 1 seconds
Started May 02 02:51:37 PM PDT 24
Finished May 02 02:51:38 PM PDT 24
Peak memory 206964 kb
Host smart-a507f63f-aed0-4269-9b55-3b428f2c70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242662238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2242662238
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3414177559
Short name T300
Test name
Test status
Simulation time 114043916 ps
CPU time 0.89 seconds
Started May 02 02:51:38 PM PDT 24
Finished May 02 02:51:40 PM PDT 24
Peak memory 215156 kb
Host smart-f354b8f2-0497-4948-8bde-b27850c2c2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414177559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3414177559
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.756691613
Short name T783
Test name
Test status
Simulation time 285203607 ps
CPU time 5.81 seconds
Started May 02 02:51:42 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 219672 kb
Host smart-8a2f0006-2cbf-42ae-928a-18b7e715aae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756691613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.756691613
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1003639093
Short name T588
Test name
Test status
Simulation time 32427121197 ps
CPU time 795.77 seconds
Started May 02 02:51:40 PM PDT 24
Finished May 02 03:04:58 PM PDT 24
Peak memory 218568 kb
Host smart-416bb2fe-8227-4183-8488-cc0e1f10ee4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003639093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1003639093
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_genbits.2414445406
Short name T387
Test name
Test status
Simulation time 28200735 ps
CPU time 1.44 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 218056 kb
Host smart-e290212c-983f-4052-a212-9b6a47231e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414445406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2414445406
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1744780737
Short name T103
Test name
Test status
Simulation time 21056574 ps
CPU time 1.2 seconds
Started May 02 02:53:30 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 229488 kb
Host smart-e1f5fd32-04d6-491a-a115-d217a2c3929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744780737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1744780737
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3089126069
Short name T453
Test name
Test status
Simulation time 83283034 ps
CPU time 1.08 seconds
Started May 02 02:53:30 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 216868 kb
Host smart-60c87d6d-33c1-4ecf-b1a1-e34ad98adcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089126069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3089126069
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1601356495
Short name T780
Test name
Test status
Simulation time 29501611 ps
CPU time 0.85 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:33 PM PDT 24
Peak memory 218404 kb
Host smart-9643cfe9-e784-4bea-bf48-675383a3fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601356495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1601356495
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1023585405
Short name T565
Test name
Test status
Simulation time 119790226 ps
CPU time 1.16 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 216896 kb
Host smart-7ca0b8fa-ff9e-4d89-8da4-353065a85b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023585405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1023585405
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.291023517
Short name T109
Test name
Test status
Simulation time 46933365 ps
CPU time 1.11 seconds
Started May 02 02:53:35 PM PDT 24
Finished May 02 02:53:38 PM PDT 24
Peak memory 229456 kb
Host smart-ba34235c-936f-4e2e-97a1-3fdab99c4c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291023517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.291023517
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4066485379
Short name T655
Test name
Test status
Simulation time 63607247 ps
CPU time 1.6 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 218272 kb
Host smart-3f8b318d-98c2-4c74-ba2f-fe69bfcfe8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066485379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4066485379
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.182479631
Short name T597
Test name
Test status
Simulation time 46565823 ps
CPU time 1.25 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 225484 kb
Host smart-394feabf-8f9a-4d94-9448-8a37a6f20e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182479631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.182479631
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3357181146
Short name T40
Test name
Test status
Simulation time 40670570 ps
CPU time 1.02 seconds
Started May 02 02:53:30 PM PDT 24
Finished May 02 02:53:32 PM PDT 24
Peak memory 215172 kb
Host smart-9ef0da63-4f08-46d9-8dd8-77d279c49f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357181146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3357181146
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.545018726
Short name T2
Test name
Test status
Simulation time 21488329 ps
CPU time 0.92 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 217788 kb
Host smart-d7b57aba-72dd-4036-a1c3-ad4dfacb8dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545018726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.545018726
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4171073177
Short name T274
Test name
Test status
Simulation time 71370172 ps
CPU time 1.58 seconds
Started May 02 02:53:33 PM PDT 24
Finished May 02 02:53:36 PM PDT 24
Peak memory 217944 kb
Host smart-56017063-0f36-4d3b-bf65-6a5f9aa885a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171073177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4171073177
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1218969889
Short name T5
Test name
Test status
Simulation time 24646624 ps
CPU time 1.3 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 229532 kb
Host smart-09d48926-dd4f-4aa8-ba26-d1ff9271500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218969889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1218969889
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.167105612
Short name T417
Test name
Test status
Simulation time 61045526 ps
CPU time 1.26 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 215244 kb
Host smart-22303d49-966f-42ac-9f0b-16f9e45069ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167105612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.167105612
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1012444033
Short name T434
Test name
Test status
Simulation time 63748443 ps
CPU time 0.99 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 218164 kb
Host smart-2b261441-190c-418c-a2ab-3ed54e708f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012444033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1012444033
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.1396093865
Short name T14
Test name
Test status
Simulation time 19284569 ps
CPU time 1.19 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 223976 kb
Host smart-f72e9b21-12f1-4041-a313-5475ca7dea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396093865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1396093865
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1134323759
Short name T781
Test name
Test status
Simulation time 155140391 ps
CPU time 1.53 seconds
Started May 02 02:53:31 PM PDT 24
Finished May 02 02:53:34 PM PDT 24
Peak memory 218120 kb
Host smart-7fdf58d6-00f0-4eef-ab00-1c9b9fed79e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134323759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1134323759
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3567141806
Short name T360
Test name
Test status
Simulation time 48109939 ps
CPU time 1.12 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 219460 kb
Host smart-93521d67-4c3a-44b1-ab30-5dfb7511fcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567141806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3567141806
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.285071734
Short name T80
Test name
Test status
Simulation time 36669441 ps
CPU time 1.71 seconds
Started May 02 02:53:32 PM PDT 24
Finished May 02 02:53:35 PM PDT 24
Peak memory 218156 kb
Host smart-4ca847a0-adc6-45aa-8883-2518c8f51e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285071734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.285071734
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3564111514
Short name T134
Test name
Test status
Simulation time 25387210 ps
CPU time 1.16 seconds
Started May 02 02:51:48 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 215564 kb
Host smart-12c73440-23ae-45ba-b690-22f93ba0548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564111514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3564111514
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3944558421
Short name T65
Test name
Test status
Simulation time 126541397 ps
CPU time 0.9 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 02:51:47 PM PDT 24
Peak memory 214496 kb
Host smart-7439f63c-1491-4812-bd91-c5ddce99a0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944558421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3944558421
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.910586670
Short name T377
Test name
Test status
Simulation time 38836017 ps
CPU time 0.8 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 215716 kb
Host smart-871a7ea7-fb43-4b4a-b903-b6f4df5c4281
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910586670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.910586670
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2597427848
Short name T464
Test name
Test status
Simulation time 19901455 ps
CPU time 1.05 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:55 PM PDT 24
Peak memory 218076 kb
Host smart-e4735eb5-e80c-4a3a-8abb-956cacf3c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597427848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2597427848
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.672145991
Short name T767
Test name
Test status
Simulation time 45259684 ps
CPU time 1.47 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 217992 kb
Host smart-b72abf32-a9dd-4788-9431-0b676d715c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672145991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.672145991
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_smoke.3936682877
Short name T59
Test name
Test status
Simulation time 19439889 ps
CPU time 0.99 seconds
Started May 02 02:51:42 PM PDT 24
Finished May 02 02:51:44 PM PDT 24
Peak memory 215168 kb
Host smart-cb7ca5a8-361d-4487-a211-ab6c95192460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936682877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3936682877
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1449490224
Short name T171
Test name
Test status
Simulation time 36359668 ps
CPU time 1.22 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:54 PM PDT 24
Peak memory 215120 kb
Host smart-371c8813-c8d0-410c-959e-cbea73a174c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449490224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1449490224
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.851343566
Short name T801
Test name
Test status
Simulation time 70993036812 ps
CPU time 1820.41 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 03:22:08 PM PDT 24
Peak memory 226996 kb
Host smart-7c0df40c-97a0-4226-8322-1109e3f337f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851343566 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.851343566
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.351401544
Short name T133
Test name
Test status
Simulation time 19779236 ps
CPU time 1.05 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 218152 kb
Host smart-5558ce87-77b4-43dd-a241-afdd4f4b4954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351401544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.351401544
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2002561505
Short name T469
Test name
Test status
Simulation time 22105534 ps
CPU time 1.23 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 217008 kb
Host smart-2732ea07-09e2-4027-b0b0-d1947d22af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002561505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2002561505
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.4011518958
Short name T100
Test name
Test status
Simulation time 20364919 ps
CPU time 1.26 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 229476 kb
Host smart-6b4b0598-13f6-4e75-8b9c-360d524fa940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011518958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4011518958
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1400216934
Short name T157
Test name
Test status
Simulation time 34989550 ps
CPU time 1.29 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 216952 kb
Host smart-bcbddd64-43f3-436a-9828-7d91e5a306e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400216934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1400216934
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1395669501
Short name T441
Test name
Test status
Simulation time 21630875 ps
CPU time 1.11 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 218348 kb
Host smart-8743cf76-a043-47f8-92c1-a4b68a420b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395669501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1395669501
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2291990293
Short name T573
Test name
Test status
Simulation time 80504517 ps
CPU time 1.03 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:40 PM PDT 24
Peak memory 216964 kb
Host smart-d3947eed-cd2d-4056-a650-454408f41e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291990293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2291990293
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1615708441
Short name T666
Test name
Test status
Simulation time 33649085 ps
CPU time 1.5 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 225504 kb
Host smart-d3a9093f-fabb-4267-8327-d93f3f579f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615708441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1615708441
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.3267763598
Short name T721
Test name
Test status
Simulation time 24186300 ps
CPU time 0.89 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:42 PM PDT 24
Peak memory 217888 kb
Host smart-5b209428-32c2-4e28-8c2b-9490231c1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267763598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3267763598
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.915660091
Short name T775
Test name
Test status
Simulation time 74378523 ps
CPU time 1.69 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 218244 kb
Host smart-8d95a188-44d6-4bf0-ae90-c733ebb472d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915660091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.915660091
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1284630595
Short name T153
Test name
Test status
Simulation time 45539948 ps
CPU time 1.21 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 219688 kb
Host smart-18918b3a-4ac1-48f9-9d7a-bcaa80dcc0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284630595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1284630595
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3680922101
Short name T622
Test name
Test status
Simulation time 48977277 ps
CPU time 1.7 seconds
Started May 02 02:53:46 PM PDT 24
Finished May 02 02:53:49 PM PDT 24
Peak memory 219560 kb
Host smart-7a4e1d63-cf17-4ded-9db1-3d957b760130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680922101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3680922101
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.4071144143
Short name T672
Test name
Test status
Simulation time 27850082 ps
CPU time 0.92 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:39 PM PDT 24
Peak memory 223716 kb
Host smart-d2197867-a999-48d9-8e72-61c96c6200f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071144143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4071144143
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1440663636
Short name T802
Test name
Test status
Simulation time 38266396 ps
CPU time 1.54 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 218180 kb
Host smart-ea0515e1-4b97-4e0a-805a-1668b675d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440663636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1440663636
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2661298960
Short name T455
Test name
Test status
Simulation time 26305394 ps
CPU time 1.35 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 232088 kb
Host smart-5553d298-658a-4406-aa3f-3bba117ecbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661298960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2661298960
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4167603326
Short name T79
Test name
Test status
Simulation time 25543218 ps
CPU time 1.2 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:40 PM PDT 24
Peak memory 216948 kb
Host smart-5e156a90-b32e-4b69-9f63-a934f5175250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167603326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4167603326
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1675329353
Short name T688
Test name
Test status
Simulation time 18478932 ps
CPU time 1.16 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 223876 kb
Host smart-fd5ffdfb-9dc0-4e9c-9666-36e7d58c6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675329353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1675329353
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2670579858
Short name T808
Test name
Test status
Simulation time 80671332 ps
CPU time 1.41 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 216828 kb
Host smart-d559f8d0-b0cb-49a8-ad2f-27017c40feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670579858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2670579858
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.426349711
Short name T113
Test name
Test status
Simulation time 24886892 ps
CPU time 1.13 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 223856 kb
Host smart-d83b45b2-9edb-447f-8c4b-4a419d27c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426349711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.426349711
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.60314812
Short name T561
Test name
Test status
Simulation time 69574491 ps
CPU time 2.42 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:44 PM PDT 24
Peak memory 219660 kb
Host smart-8684c58f-b9f3-470a-a290-40e5d323a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60314812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.60314812
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4186854400
Short name T246
Test name
Test status
Simulation time 25365375 ps
CPU time 1.26 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:55 PM PDT 24
Peak memory 215480 kb
Host smart-18e59b42-4de0-4b6c-9950-bd864433256c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186854400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4186854400
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3219335738
Short name T773
Test name
Test status
Simulation time 19964770 ps
CPU time 1.06 seconds
Started May 02 02:51:50 PM PDT 24
Finished May 02 02:51:52 PM PDT 24
Peak memory 206540 kb
Host smart-76731633-c683-4246-b6c3-a13b2ede80e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219335738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3219335738
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2614653811
Short name T148
Test name
Test status
Simulation time 39828514 ps
CPU time 0.85 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 02:51:48 PM PDT 24
Peak memory 216028 kb
Host smart-5aec7aba-f4fc-4622-a72d-cd2a07fa2f81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614653811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2614653811
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3454657510
Short name T111
Test name
Test status
Simulation time 33043312 ps
CPU time 0.95 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:54 PM PDT 24
Peak memory 218012 kb
Host smart-0381c4d5-80df-41eb-a2fc-ac64da06acb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454657510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3454657510
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2660689436
Short name T706
Test name
Test status
Simulation time 19212353 ps
CPU time 1.01 seconds
Started May 02 02:51:45 PM PDT 24
Finished May 02 02:51:47 PM PDT 24
Peak memory 218008 kb
Host smart-50932994-b439-4f0b-8833-ef18ad41d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660689436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2660689436
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1795018626
Short name T510
Test name
Test status
Simulation time 38626907 ps
CPU time 1.79 seconds
Started May 02 02:51:50 PM PDT 24
Finished May 02 02:51:53 PM PDT 24
Peak memory 218192 kb
Host smart-5ea7fdfd-de16-4e51-9e71-99fccde1beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795018626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1795018626
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1546749639
Short name T549
Test name
Test status
Simulation time 66696137 ps
CPU time 0.79 seconds
Started May 02 02:51:49 PM PDT 24
Finished May 02 02:51:51 PM PDT 24
Peak memory 215436 kb
Host smart-e3422524-ec9b-4389-8ae2-aaf677c6b800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546749639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1546749639
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.3723057297
Short name T537
Test name
Test status
Simulation time 39808426 ps
CPU time 0.92 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:55 PM PDT 24
Peak memory 215120 kb
Host smart-54497a37-b9d9-4c9e-b507-65fd9e082463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723057297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3723057297
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1196936546
Short name T702
Test name
Test status
Simulation time 231109469 ps
CPU time 2.68 seconds
Started May 02 02:51:51 PM PDT 24
Finished May 02 02:51:54 PM PDT 24
Peak memory 216696 kb
Host smart-221db0e2-7b58-4659-a45b-5e234b4fb91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196936546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1196936546
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3230498835
Short name T208
Test name
Test status
Simulation time 40942600763 ps
CPU time 906.73 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 03:06:54 PM PDT 24
Peak memory 218424 kb
Host smart-02b68af0-ab8e-4fcc-a142-fbe50fc845d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230498835 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3230498835
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.205124475
Short name T811
Test name
Test status
Simulation time 39506928 ps
CPU time 0.87 seconds
Started May 02 02:53:36 PM PDT 24
Finished May 02 02:53:38 PM PDT 24
Peak memory 218116 kb
Host smart-c6e7e619-3106-4d48-b63c-69ac8b7d2fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205124475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.205124475
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2997500983
Short name T577
Test name
Test status
Simulation time 62101160 ps
CPU time 1.04 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:42 PM PDT 24
Peak memory 216836 kb
Host smart-e1ce06d9-e5b6-49cb-a0a7-95ae0827dcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997500983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2997500983
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3912510471
Short name T459
Test name
Test status
Simulation time 19852837 ps
CPU time 1.11 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:40 PM PDT 24
Peak memory 218144 kb
Host smart-12ec990e-6df5-4bcd-8307-f772533c152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912510471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3912510471
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2995762431
Short name T335
Test name
Test status
Simulation time 83555398 ps
CPU time 1.12 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:39 PM PDT 24
Peak memory 219192 kb
Host smart-a853f0ef-a2a7-4a68-809f-41f013fefceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995762431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2995762431
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2456923735
Short name T550
Test name
Test status
Simulation time 19030071 ps
CPU time 1.04 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 218460 kb
Host smart-4c28aea3-a962-4aff-ac4f-5ade3b01da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456923735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2456923735
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3009260733
Short name T92
Test name
Test status
Simulation time 84579065 ps
CPU time 2.81 seconds
Started May 02 02:53:41 PM PDT 24
Finished May 02 02:53:45 PM PDT 24
Peak memory 218072 kb
Host smart-5c8ecd6c-048c-42bd-8ec7-b65cfcd64f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009260733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3009260733
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1703713188
Short name T127
Test name
Test status
Simulation time 23350319 ps
CPU time 1.02 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:39 PM PDT 24
Peak memory 223896 kb
Host smart-558e2288-15d5-4788-b036-eae4bad33348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703713188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1703713188
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3232993438
Short name T764
Test name
Test status
Simulation time 65295310 ps
CPU time 2.18 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:40 PM PDT 24
Peak memory 219308 kb
Host smart-1dcfdf6b-977d-42dc-bb6b-c98ef6bbcbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232993438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3232993438
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.696380607
Short name T185
Test name
Test status
Simulation time 30907746 ps
CPU time 1.24 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:44 PM PDT 24
Peak memory 220604 kb
Host smart-96d7f72a-7289-4e71-a0d9-dd4e2cd83436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696380607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.696380607
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4080578474
Short name T347
Test name
Test status
Simulation time 104350987 ps
CPU time 1.26 seconds
Started May 02 02:53:37 PM PDT 24
Finished May 02 02:53:39 PM PDT 24
Peak memory 218008 kb
Host smart-995a7277-db56-4612-b12c-a97d10fb28d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080578474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4080578474
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1995518058
Short name T518
Test name
Test status
Simulation time 30947283 ps
CPU time 0.91 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:42 PM PDT 24
Peak memory 219664 kb
Host smart-fbcc64c4-f064-4353-86e5-5dbe40b5d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995518058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1995518058
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.683046503
Short name T657
Test name
Test status
Simulation time 64628389 ps
CPU time 0.97 seconds
Started May 02 02:53:40 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 216728 kb
Host smart-39de95cc-bd9e-4ae3-af6b-f6155cf75f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683046503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.683046503
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3763544026
Short name T75
Test name
Test status
Simulation time 24974246 ps
CPU time 0.94 seconds
Started May 02 02:53:39 PM PDT 24
Finished May 02 02:53:43 PM PDT 24
Peak memory 218548 kb
Host smart-6db0c3c1-f099-4e08-80ab-6de04bf931f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763544026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3763544026
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3244804824
Short name T581
Test name
Test status
Simulation time 112606966 ps
CPU time 1.61 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 219980 kb
Host smart-b92deadb-3ba2-4c55-aa30-b5dd96c2ef5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244804824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3244804824
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1914881185
Short name T203
Test name
Test status
Simulation time 22006876 ps
CPU time 0.9 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:40 PM PDT 24
Peak memory 217916 kb
Host smart-fc47b948-bda4-4c95-9fbb-6a82a2458d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914881185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1914881185
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1814210185
Short name T824
Test name
Test status
Simulation time 60648988 ps
CPU time 1.25 seconds
Started May 02 02:53:38 PM PDT 24
Finished May 02 02:53:41 PM PDT 24
Peak memory 216804 kb
Host smart-06db79f8-e7cd-4c17-a728-7865df5ce99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814210185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1814210185
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.422091415
Short name T614
Test name
Test status
Simulation time 19100215 ps
CPU time 1.04 seconds
Started May 02 02:53:42 PM PDT 24
Finished May 02 02:53:44 PM PDT 24
Peak memory 218048 kb
Host smart-be8c1876-bfab-4813-94a9-92ffe64081fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422091415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.422091415
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.317385491
Short name T85
Test name
Test status
Simulation time 80592654 ps
CPU time 2.8 seconds
Started May 02 02:53:42 PM PDT 24
Finished May 02 02:53:47 PM PDT 24
Peak memory 219772 kb
Host smart-27e3dfa9-a118-462f-9fc5-f2cd19c962b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317385491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.317385491
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1105862748
Short name T696
Test name
Test status
Simulation time 72385641 ps
CPU time 1.06 seconds
Started May 02 02:53:51 PM PDT 24
Finished May 02 02:53:55 PM PDT 24
Peak memory 219664 kb
Host smart-e56c64d5-373b-4924-9f0e-17875cdf22f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105862748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1105862748
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4274840845
Short name T758
Test name
Test status
Simulation time 181788895 ps
CPU time 1.39 seconds
Started May 02 02:53:46 PM PDT 24
Finished May 02 02:53:48 PM PDT 24
Peak memory 218328 kb
Host smart-77e75bbb-2d60-490e-9f3c-deaeca2d10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274840845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4274840845
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3210308171
Short name T799
Test name
Test status
Simulation time 195317970 ps
CPU time 1.22 seconds
Started May 02 02:51:49 PM PDT 24
Finished May 02 02:51:52 PM PDT 24
Peak memory 215500 kb
Host smart-3159f403-6ca6-4cc2-93f2-dd16bd2b2fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210308171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3210308171
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2570835286
Short name T432
Test name
Test status
Simulation time 16028465 ps
CPU time 0.97 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:54 PM PDT 24
Peak memory 215012 kb
Host smart-a82419c4-93d7-44b0-b9af-59ae8e65beb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570835286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2570835286
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3473819572
Short name T144
Test name
Test status
Simulation time 15790086 ps
CPU time 0.8 seconds
Started May 02 02:51:51 PM PDT 24
Finished May 02 02:51:53 PM PDT 24
Peak memory 216000 kb
Host smart-006069d0-fc02-4827-ba82-23eee7775e69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473819572 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3473819572
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3612473587
Short name T409
Test name
Test status
Simulation time 49659137 ps
CPU time 1.14 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 219300 kb
Host smart-8877489e-b12d-4b8a-9aa3-b9b420082237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612473587 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3612473587
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2025198666
Short name T123
Test name
Test status
Simulation time 29584477 ps
CPU time 0.99 seconds
Started May 02 02:51:49 PM PDT 24
Finished May 02 02:51:51 PM PDT 24
Peak memory 223672 kb
Host smart-17604adf-be59-47ca-8f85-62a070239e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025198666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2025198666
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.376910076
Short name T428
Test name
Test status
Simulation time 248683215 ps
CPU time 1.17 seconds
Started May 02 02:51:51 PM PDT 24
Finished May 02 02:51:54 PM PDT 24
Peak memory 216928 kb
Host smart-0f35eec8-6877-4ff5-9acd-52bb78a5532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376910076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.376910076
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.612537129
Short name T98
Test name
Test status
Simulation time 28884097 ps
CPU time 0.87 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:49 PM PDT 24
Peak memory 215548 kb
Host smart-260a1566-fedf-453b-a2aa-85faf69fcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612537129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.612537129
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1256198668
Short name T255
Test name
Test status
Simulation time 44524375 ps
CPU time 0.9 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 02:51:50 PM PDT 24
Peak memory 206940 kb
Host smart-f2192129-4db7-4f7c-a171-deb106d4c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256198668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1256198668
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2450799230
Short name T391
Test name
Test status
Simulation time 24469475 ps
CPU time 0.89 seconds
Started May 02 02:51:46 PM PDT 24
Finished May 02 02:51:47 PM PDT 24
Peak memory 215164 kb
Host smart-089da1b0-c398-4f9e-ad86-22c10bc8d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450799230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2450799230
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1535865540
Short name T63
Test name
Test status
Simulation time 266877440 ps
CPU time 3.15 seconds
Started May 02 02:51:52 PM PDT 24
Finished May 02 02:51:56 PM PDT 24
Peak memory 216844 kb
Host smart-77f1c5a7-31f2-41f9-845c-89f068e83247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535865540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1535865540
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2500245475
Short name T751
Test name
Test status
Simulation time 225456832370 ps
CPU time 941.86 seconds
Started May 02 02:51:47 PM PDT 24
Finished May 02 03:07:30 PM PDT 24
Peak memory 221744 kb
Host smart-ac02974a-3a41-4912-abe1-c79b17ae09d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500245475 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2500245475
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3886641929
Short name T119
Test name
Test status
Simulation time 21539349 ps
CPU time 1.13 seconds
Started May 02 02:53:45 PM PDT 24
Finished May 02 02:53:48 PM PDT 24
Peak memory 219492 kb
Host smart-1baac83f-5b0f-479c-8881-2610d68e1cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886641929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3886641929
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.223044634
Short name T519
Test name
Test status
Simulation time 42074087 ps
CPU time 1.44 seconds
Started May 02 02:53:46 PM PDT 24
Finished May 02 02:53:49 PM PDT 24
Peak memory 218084 kb
Host smart-4bb55cf4-a09a-4ca0-8632-bfea5ab1d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223044634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.223044634
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.747395793
Short name T141
Test name
Test status
Simulation time 29722402 ps
CPU time 1 seconds
Started May 02 02:53:42 PM PDT 24
Finished May 02 02:53:44 PM PDT 24
Peak memory 218164 kb
Host smart-0d9ab88f-bfd6-4a5f-9659-5972669b817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747395793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.747395793
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3436473060
Short name T667
Test name
Test status
Simulation time 50851144 ps
CPU time 1.54 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 216936 kb
Host smart-fb8874d8-fd55-41d5-8824-23e4ad5565b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436473060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3436473060
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1704792406
Short name T307
Test name
Test status
Simulation time 21754289 ps
CPU time 0.89 seconds
Started May 02 02:53:42 PM PDT 24
Finished May 02 02:53:45 PM PDT 24
Peak memory 218368 kb
Host smart-3853e739-a93f-42eb-ba66-e7886ae3f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704792406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1704792406
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3458980873
Short name T804
Test name
Test status
Simulation time 101160107 ps
CPU time 1.11 seconds
Started May 02 02:53:44 PM PDT 24
Finished May 02 02:53:47 PM PDT 24
Peak memory 217008 kb
Host smart-365a55d2-e553-4fee-be99-b45f6dda6942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458980873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3458980873
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.273295209
Short name T139
Test name
Test status
Simulation time 28122510 ps
CPU time 0.83 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:50 PM PDT 24
Peak memory 218048 kb
Host smart-248c1b59-0118-4e7e-9173-b1ba2d47f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273295209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.273295209
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2014623218
Short name T660
Test name
Test status
Simulation time 52218835 ps
CPU time 1.25 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 217140 kb
Host smart-b96e208d-478b-4b04-b133-d86113ad9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014623218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2014623218
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3355433386
Short name T136
Test name
Test status
Simulation time 22434041 ps
CPU time 1.18 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:45 PM PDT 24
Peak memory 223872 kb
Host smart-4324dece-658c-4033-9176-ae885325c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355433386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3355433386
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3303834923
Short name T316
Test name
Test status
Simulation time 45136355 ps
CPU time 1.39 seconds
Started May 02 02:53:44 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 217928 kb
Host smart-b9e53f4a-996a-4756-9dfc-fe9d14b947ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303834923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3303834923
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2542324746
Short name T7
Test name
Test status
Simulation time 48306922 ps
CPU time 1.05 seconds
Started May 02 02:53:45 PM PDT 24
Finished May 02 02:53:48 PM PDT 24
Peak memory 229424 kb
Host smart-965cad1e-6f6a-41cf-ac78-e5a8cd55f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542324746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2542324746
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1209196606
Short name T485
Test name
Test status
Simulation time 36097277 ps
CPU time 1.5 seconds
Started May 02 02:53:47 PM PDT 24
Finished May 02 02:53:50 PM PDT 24
Peak memory 218236 kb
Host smart-d574d66c-e464-441f-b60e-ebfd13a59a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209196606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1209196606
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.360321785
Short name T753
Test name
Test status
Simulation time 61596765 ps
CPU time 1.18 seconds
Started May 02 02:53:46 PM PDT 24
Finished May 02 02:53:49 PM PDT 24
Peak memory 229680 kb
Host smart-e4833aa3-d08c-4ab2-a7d5-84bddbfe6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360321785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.360321785
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1801256319
Short name T743
Test name
Test status
Simulation time 33891897 ps
CPU time 1.35 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 219324 kb
Host smart-40684b07-4484-41c2-bb30-41e71366f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801256319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1801256319
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2997135645
Short name T716
Test name
Test status
Simulation time 28811281 ps
CPU time 0.84 seconds
Started May 02 02:53:44 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 217892 kb
Host smart-80ac0fac-5152-4f92-a4b0-1181fb524229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997135645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2997135645
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.933278126
Short name T389
Test name
Test status
Simulation time 48343629 ps
CPU time 2.03 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:52 PM PDT 24
Peak memory 217352 kb
Host smart-4dc4654b-a562-4b0f-9963-0f78cdfebddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933278126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.933278126
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3393474910
Short name T568
Test name
Test status
Simulation time 21717259 ps
CPU time 0.95 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:45 PM PDT 24
Peak memory 217952 kb
Host smart-4077d697-0d9f-415e-b8b5-757e427fe9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393474910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3393474910
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.406750147
Short name T564
Test name
Test status
Simulation time 31504851 ps
CPU time 1.29 seconds
Started May 02 02:53:43 PM PDT 24
Finished May 02 02:53:46 PM PDT 24
Peak memory 218128 kb
Host smart-b4b16ee2-de65-45f1-a0ca-a90ca3e068e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406750147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.406750147
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1659020678
Short name T527
Test name
Test status
Simulation time 32772547 ps
CPU time 0.85 seconds
Started May 02 02:53:49 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 218364 kb
Host smart-3050c051-98f3-4ce9-bfa2-d71f84ba292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659020678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1659020678
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.223434313
Short name T256
Test name
Test status
Simulation time 50913808 ps
CPU time 1.84 seconds
Started May 02 02:53:48 PM PDT 24
Finished May 02 02:53:51 PM PDT 24
Peak memory 218172 kb
Host smart-a4bda811-47b9-4e65-a85e-9fc89b20eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223434313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.223434313
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%