---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.RoundRobin_A	0	0	227365895	0	0	809

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertTxKnownO_A	0	0	227365895	227198914	0	0
tb.dut.CsrngAppIfOut_A	0	0	227365895	227198914	0	0
tb.dut.FpvSecCmCntAlertCheck_A	0	0	227365895	116	0	0
tb.dut.FpvSecCmGenCmdFifoRptrCheck_A	0	0	227365895	70	0	0
tb.dut.FpvSecCmGenCmdFifoWptrCheck_A	0	0	227365895	70	0	0
tb.dut.FpvSecCmMainFsmCheck_A	0	0	227365895	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	227365895	70	0	0
tb.dut.FpvSecCmResCmdFifoRptrCheck_A	0	0	227365895	70	0	0
tb.dut.FpvSecCmResCmdFifoWptrCheck_A	0	0	227365895	70	0	0
tb.dut.IntrEdnCmdReqDoneKnownO_A	0	0	227365895	227198914	0	0
tb.dut.TlAReadyKnownO_A	0	0	227365895	227198914	0	0
tb.dut.TlDValidKnownO_A	0	0	227365895	227198914	0	0
tb.dut.edn_csr_assert.TlulOOBAddrErr_A	0	0	227860550	10404453	0	0
tb.dut.edn_csr_assert.boot_gen_cmd_rd_A	0	0	227860550	57168	0	0
tb.dut.edn_csr_assert.boot_ins_cmd_rd_A	0	0	227860550	67278	0	0
tb.dut.edn_csr_assert.ctrl_rd_A	0	0	227860550	57761	0	0
tb.dut.edn_csr_assert.err_code_test_rd_A	0	0	227860550	66489	0	0
tb.dut.edn_csr_assert.intr_enable_rd_A	0	0	227860550	65370	0	0
tb.dut.edn_csr_assert.max_num_reqs_between_reseeds_rd_A	0	0	227860550	58700	0	0
tb.dut.edn_csr_assert.regwen_rd_A	0	0	227860550	67363	0	0
tb.dut.gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	0	0	227365895	70	0	0
tb.dut.gen_edn_if_asserts[0].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[0].EdnDataStable_A	0	0	227365895	24932	0	348
tb.dut.gen_edn_if_asserts[0].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[1].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[1].EdnDataStable_A	0	0	227365895	5432	0	118
tb.dut.gen_edn_if_asserts[1].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[2].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[2].EdnDataStable_A	0	0	227365895	5175	0	103
tb.dut.gen_edn_if_asserts[2].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[3].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[3].EdnDataStable_A	0	0	227365895	4174	0	102
tb.dut.gen_edn_if_asserts[3].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[4].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[4].EdnDataStable_A	0	0	227365895	4134	0	106
tb.dut.gen_edn_if_asserts[4].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[5].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[5].EdnDataStable_A	0	0	227365895	2810	0	77
tb.dut.gen_edn_if_asserts[5].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.gen_edn_if_asserts[6].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[6].EdnDataStable_A	0	0	227365895	1101	0	75
tb.dut.gen_edn_if_asserts[6].EdnEndPointOut_A	0	0	227365895	227198914	0	0
tb.dut.gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	0	0	227365895	152078	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	227860550	34480438	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	227860550	227655333	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	227860550	227655333	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	227860550	33109189	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	227860550	227655333	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	227860550	227655333	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	974	974	0	0
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tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	227860550	4799591	0	0
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tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	227861159	110457	0	0
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tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	227861159	34480438	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	227861159	33109189	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	227861159	34480438	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	227861159	33109189	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	227861159	33109189	0	0
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tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	227860550	2870882	0	0
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tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	974	974	0	0
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tb.dut.u_edn_core.CsErrIssueNoCommands_A	0	0	227365895	6936	0	0
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tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.FpvSecCmErrorStEscalate_A	0	0	227365895	150723	0	0
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep.u_state_regs_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	197482	0	809
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep.ValidOPairedWithReadyI_A	0	0	227365895	197482	0	0
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.AckSmErrorStStable_A	0	0	227365895	149680	0	0
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.FpvSecCmErrorStEscalate_A	0	0	227365895	150723	0	0
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep.u_state_regs_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	199399	0	809
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep.ValidOPairedWithReadyI_A	0	0	227365895	199399	0	0
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.AckSmErrorStStable_A	0	0	227365895	149680	0	0
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.FpvSecCmErrorStEscalate_A	0	0	227365895	150723	0	0
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep.u_state_regs_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	221252	0	809
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep.ValidOPairedWithReadyI_A	0	0	227365895	221252	0	0
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.AckSmErrorStStable_A	0	0	227365895	149680	0	0
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.FpvSecCmErrorStEscalate_A	0	0	227365895	150723	0	0
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep.u_state_regs_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	157198	0	809
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep.ValidOPairedWithReadyI_A	0	0	227365895	157198	0	0
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.AckSmErrorStStable_A	0	0	227365895	149680	0	0
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.FpvSecCmErrorStEscalate_A	0	0	227365895	150723	0	0
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep.u_state_regs_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	150159	0	809
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep.ValidOPairedWithReadyI_A	0	0	227365895	150159	0	0
tb.dut.u_edn_core.u_edn_main_sm.ErrorStStable_A	0	0	227365895	147530	0	0
tb.dut.u_edn_core.u_edn_main_sm.FpvSecCmErrorStEscalate_A	0	0	227365895	148573	0	0
tb.dut.u_edn_core.u_edn_main_sm.u_state_regs.AssertConnected_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_edn_main_sm.u_state_regs_A	0	0	227323175	227156194	0	0
tb.dut.u_edn_core.u_intr_hw_edn_cmd_req_done.IntrTKind_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_intr_hw_edn_fatal_err.IntrTKind_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.CheckHotOne_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.CheckNGreaterZero_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.GntImpliesReady_A	0	0	227365895	12505	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.GntImpliesValid_A	0	0	227365895	12505	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.GrantKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.IdxKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.IndexIsCorrect_A	0	0	227365895	12505	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.LockArbDecision_A	0	0	227365895	648785	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.NoReadyValidNoGrant_A	0	0	227365895	226462123	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.ReadyAndValidImplyGrant_A	0	0	227365895	12505	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.ReqAndReadyImplyGrant_A	0	0	227365895	12505	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.ReqImpliesValid_A	0	0	227365895	662286	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.ReqStaysHighUntilGranted0_M	0	0	227365895	648785	0	0
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.ValidKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.DataKnown_A	0	0	226987277	288335	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.DepthKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.RvalidKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.WreadyKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	227186825	337090	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.DataKnown_A	0	0	226987277	278105	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.DepthKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.RvalidKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.WreadyKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	227186825	326743	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.NumCopiesMustBeGreaterZero_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.OutputsKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode.gen_no_flops.OutputDelay_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.NumCopiesMustBeGreaterZero_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.OutputsKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode.gen_no_flops.OutputDelay_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.NumCopiesMustBeGreaterZero_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.OutputsKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst.gen_no_flops.OutputDelay_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.NumCopiesMustBeGreaterZero_A	0	0	809	809	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.OutputsKnown_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_no_flops.OutputDelay_A	0	0	227365895	227198914	0	0
tb.dut.u_edn_core.u_prim_packer_fifo_cs.DataOStableWhenPending_A	0	0	227365895	74429	0	809
tb.dut.u_edn_core.u_prim_packer_fifo_cs.ValidOPairedWithReadyI_A	0	0	227365895	74429	0	0
tb.dut.u_reg.en2addrHit	0	0	227860550	797914	0	0
tb.dut.u_reg.reAfterRv	0	0	227860550	797914	0	0
tb.dut.u_reg.rePulse	0	0	227860550	301213	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	974	974	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	974	974	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	974	974	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	974	974	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	974	974	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	974	974	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	974	974	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	974	974	0	0
tb.dut.u_reg.wePulse	0	0	227860550	496701	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_edn_if_asserts[0].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[0].EdnDataStable_A	0	0	227365895	24932	0	348
tb.dut.gen_edn_if_asserts[1].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[1].EdnDataStable_A	0	0	227365895	5432	0	118
tb.dut.gen_edn_if_asserts[2].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[2].EdnDataStable_A	0	0	227365895	5175	0	103
tb.dut.gen_edn_if_asserts[3].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[3].EdnDataStable_A	0	0	227365895	4174	0	102
tb.dut.gen_edn_if_asserts[4].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[4].EdnDataStable_A	0	0	227365895	4134	0	106
tb.dut.gen_edn_if_asserts[5].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[5].EdnDataStable_A	0	0	227365895	2810	0	77
tb.dut.gen_edn_if_asserts[6].EdnDataStableDisable_A	0	0	227365895	553384	0	304
tb.dut.gen_edn_if_asserts[6].EdnDataStable_A	0	0	227365895	1101	0	75
tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	203212121	0	809
tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	253588	0	809
tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	197482	0	809
tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	199399	0	809
tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	221252	0	809
tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	157198	0	809
tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep.DataOStableWhenPending_A	0	0	227365895	150159	0	809
tb.dut.u_edn_core.u_prim_arbiter_ppc_packer_arb.RoundRobin_A	0	0	227365895	0	0	809
tb.dut.u_edn_core.u_prim_packer_fifo_cs.DataOStableWhenPending_A	0	0	227365895	74429	0	809

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	227861159	272	272	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	227861159	39	39	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	227861159	41	41	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	227861159	30	30	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	227861159	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	227861159	24	24	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	227861159	23	23	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	227861159	1466	1466	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	227861159	2478	2478	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	227861159	54171	54171	910

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	227861159	272	272	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	227861159	39	39	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	227861159	41	41	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	227861159	30	30	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	227861159	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	227861159	24	24	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	227861159	23	23	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	227861159	1466	1466	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	227861159	2478	2478	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	227861159	54171	54171	910