Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	702756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5751445

1

T1

15402

T2

49670

T3

73

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1697352	1			T1	5275		T2	14225		T3	19
values[0x0]	2198448	1			T1	5867		T2	19048		T3	40
values[0x1]	2558401	1			T1	6760		T2	21830		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	343963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6110238

1

T1

16400

T2

52636

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24923	1			T1	41		T2	392		T4	4
valid_sources[0x01]	26931	1			T1	72		T8	159		T4	1
valid_sources[0x02]	24757	1			T1	71		T2	28		T4	1
valid_sources[0x03]	26657	1			T1	120		T2	533		T4	6
valid_sources[0x04]	26164	1			T1	60		T2	144		T4	1
valid_sources[0x05]	26829	1			T1	54		T2	334		T4	5
valid_sources[0x06]	22389	1			T1	55		T2	1		T4	3
valid_sources[0x07]	24456	1			T1	65		T2	7		T4	3
valid_sources[0x08]	26610	1			T1	78		T2	170		T4	3
valid_sources[0x09]	24904	1			T1	67		T2	17		T4	3
valid_sources[0x0a]	25459	1			T1	61		T2	44		T4	5
valid_sources[0x0b]	23999	1			T1	48		T2	104		T4	3
valid_sources[0x0c]	24126	1			T1	69		T2	239		T4	3
valid_sources[0x0d]	23844	1			T1	70		T4	4		T83	4
valid_sources[0x0e]	25237	1			T1	76		T2	258		T4	5
valid_sources[0x0f]	24967	1			T1	60		T2	179		T4	5
valid_sources[0x10]	24637	1			T1	69		T2	148		T4	3
valid_sources[0x11]	24719	1			T1	64		T2	40		T4	5
valid_sources[0x12]	25898	1			T1	69		T2	215		T4	2
valid_sources[0x13]	25397	1			T1	77		T2	129		T4	1
valid_sources[0x14]	27140	1			T1	45		T2	675		T4	2
valid_sources[0x15]	24614	1			T1	80		T2	776		T4	3
valid_sources[0x16]	24559	1			T1	56		T2	416		T4	1
valid_sources[0x17]	26580	1			T1	90		T2	442		T4	4
valid_sources[0x18]	28020	1			T1	101		T2	126		T4	5
valid_sources[0x19]	26326	1			T1	119		T2	223		T4	4
valid_sources[0x1a]	25213	1			T1	58		T2	249		T4	4
valid_sources[0x1b]	24586	1			T1	53		T2	13		T4	5
valid_sources[0x1c]	25727	1			T1	64		T2	116		T4	2
valid_sources[0x1d]	26190	1			T1	92		T4	2		T83	4
valid_sources[0x1e]	25798	1			T1	88		T2	149		T4	8
valid_sources[0x1f]	26688	1			T1	77		T2	122		T4	2
valid_sources[0x20]	23460	1			T1	51		T2	55		T4	2
valid_sources[0x21]	23839	1			T1	55		T2	203		T4	3
valid_sources[0x22]	23204	1			T1	70		T2	181		T4	3
valid_sources[0x23]	26164	1			T1	76		T2	7		T83	4
valid_sources[0x24]	23983	1			T1	63		T2	210		T4	2
valid_sources[0x25]	25434	1			T1	58		T4	3		T83	4
valid_sources[0x26]	26104	1			T1	98		T2	653		T4	4
valid_sources[0x27]	26647	1			T1	85		T2	304		T4	2
valid_sources[0x28]	25815	1			T1	61		T2	39		T4	3
valid_sources[0x29]	26270	1			T1	84		T2	723		T4	1
valid_sources[0x2a]	25514	1			T1	64		T2	605		T4	1
valid_sources[0x2b]	26451	1			T1	72		T2	849		T4	2
valid_sources[0x2c]	24061	1			T1	72		T2	112		T4	4
valid_sources[0x2d]	24729	1			T1	71		T2	12		T4	4
valid_sources[0x2e]	26849	1			T1	71		T2	991		T4	2
valid_sources[0x2f]	23805	1			T1	83		T2	11		T4	3
valid_sources[0x30]	25832	1			T1	67		T2	176		T4	2
valid_sources[0x31]	25503	1			T1	100		T2	217		T4	2
valid_sources[0x32]	24366	1			T1	76		T2	268		T4	6
valid_sources[0x33]	26845	1			T1	77		T2	542		T4	4
valid_sources[0x34]	26406	1			T1	44		T2	411		T4	2
valid_sources[0x35]	23657	1			T1	106		T2	175		T4	1
valid_sources[0x36]	26721	1			T1	77		T2	285		T4	2
valid_sources[0x37]	26569	1			T1	52		T2	251		T4	3
valid_sources[0x38]	23922	1			T1	79		T2	278		T4	4
valid_sources[0x39]	25542	1			T1	77		T2	106		T4	1
valid_sources[0x3a]	26145	1			T1	100		T2	108		T4	2
valid_sources[0x3b]	23958	1			T1	73		T2	66		T4	2
valid_sources[0x3c]	25127	1			T1	60		T2	267		T4	2
valid_sources[0x3d]	26322	1			T1	88		T2	540		T83	6
valid_sources[0x3e]	24879	1			T1	75		T2	129		T4	2
valid_sources[0x3f]	25009	1			T1	62		T2	310		T4	3
valid_sources[0x40]	23876	1			T1	57		T2	252		T4	3
valid_sources[0x41]	23860	1			T1	68		T2	540		T83	1
valid_sources[0x42]	23470	1			T1	48		T4	2		T83	1
valid_sources[0x43]	25364	1			T1	38		T2	547		T4	4
valid_sources[0x44]	22623	1			T1	68		T2	97		T4	1
valid_sources[0x45]	24371	1			T1	70		T2	152		T4	3
valid_sources[0x46]	25190	1			T1	87		T2	550		T4	1
valid_sources[0x47]	25668	1			T1	54		T2	173		T4	6
valid_sources[0x48]	25263	1			T1	62		T4	3		T60	1
valid_sources[0x49]	24644	1			T1	79		T2	80		T4	7
valid_sources[0x4a]	23916	1			T1	74		T2	2		T4	1
valid_sources[0x4b]	23571	1			T1	68		T2	95		T81	1
valid_sources[0x4c]	23986	1			T1	71		T4	5		T83	3
valid_sources[0x4d]	26017	1			T1	71		T2	102		T4	1
valid_sources[0x4e]	24551	1			T1	65		T2	198		T4	3
valid_sources[0x4f]	26148	1			T1	47		T2	832		T4	2
valid_sources[0x50]	24656	1			T1	55		T4	1		T83	6
valid_sources[0x51]	25690	1			T1	86		T2	227		T4	5
valid_sources[0x52]	25589	1			T1	66		T2	315		T4	5
valid_sources[0x53]	23918	1			T1	65		T2	367		T4	4
valid_sources[0x54]	26232	1			T1	66		T2	603		T4	1
valid_sources[0x55]	25405	1			T1	43		T2	776		T4	1
valid_sources[0x56]	26614	1			T1	111		T2	256		T4	5
valid_sources[0x57]	26640	1			T1	55		T2	153		T4	4
valid_sources[0x58]	25277	1			T1	77		T4	1		T83	1
valid_sources[0x59]	24821	1			T1	94		T2	160		T4	6
valid_sources[0x5a]	25653	1			T1	50		T2	226		T4	1
valid_sources[0x5b]	25617	1			T1	68		T4	2		T45	692
valid_sources[0x5c]	25883	1			T1	92		T2	359		T4	3
valid_sources[0x5d]	24048	1			T1	83		T2	183		T4	5
valid_sources[0x5e]	25667	1			T1	63		T2	497		T4	1
valid_sources[0x5f]	24927	1			T1	64		T4	2		T83	6
valid_sources[0x60]	25147	1			T1	76		T2	865		T4	3
valid_sources[0x61]	24735	1			T1	73		T4	2		T83	5
valid_sources[0x62]	24550	1			T1	60		T2	369		T4	3
valid_sources[0x63]	25039	1			T1	70		T2	156		T4	2
valid_sources[0x64]	25086	1			T1	98		T2	331		T4	5
valid_sources[0x65]	25171	1			T1	54		T2	180		T4	3
valid_sources[0x66]	24777	1			T1	82		T2	114		T4	2
valid_sources[0x67]	26032	1			T1	81		T2	255		T4	1
valid_sources[0x68]	24844	1			T1	57		T2	94		T4	3
valid_sources[0x69]	24398	1			T1	75		T2	278		T4	2
valid_sources[0x6a]	25232	1			T1	79		T4	1		T83	2
valid_sources[0x6b]	25360	1			T1	62		T2	189		T4	3
valid_sources[0x6c]	26667	1			T1	51		T2	111		T4	4
valid_sources[0x6d]	25264	1			T1	94		T2	96		T4	3
valid_sources[0x6e]	25525	1			T1	56		T2	100		T4	3
valid_sources[0x6f]	25277	1			T1	85		T4	3		T45	1148
valid_sources[0x70]	27165	1			T1	80		T2	286		T4	5
valid_sources[0x71]	25392	1			T1	90		T2	6		T4	4
valid_sources[0x72]	26093	1			T1	64		T2	128		T4	4
valid_sources[0x73]	26193	1			T1	50		T2	285		T4	4
valid_sources[0x74]	24981	1			T1	56		T2	10		T4	2
valid_sources[0x75]	25960	1			T1	56		T2	431		T4	2
valid_sources[0x76]	23772	1			T1	54		T2	66		T4	3
valid_sources[0x77]	24922	1			T1	61		T2	68		T4	5
valid_sources[0x78]	25020	1			T1	67		T4	2		T26	29
valid_sources[0x79]	25329	1			T1	40		T2	227		T4	1
valid_sources[0x7a]	26770	1			T1	80		T2	16		T4	3
valid_sources[0x7b]	26969	1			T1	56		T2	1064		T81	2
valid_sources[0x7c]	23841	1			T1	77		T2	98		T4	3
valid_sources[0x7d]	26132	1			T1	107		T2	236		T4	1
valid_sources[0x7e]	24742	1			T1	64		T2	351		T4	6
valid_sources[0x7f]	24057	1			T1	93		T2	106		T4	2
valid_sources[0x80]	25112	1			T1	53		T2	463		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1446797

1

T1

3936

T2

12639

T3

2

values[0x0]

all_enables

biggest_size

2153660

1

T1

5669

T2

18679

T3

38

values[0x1]

all_enables

biggest_size

2150988

1

T1

5797

T2

18352

T3

33