Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2613	1			T1	36		T2	13		T3	3
non_zero_bins[1]	1816	1			T1	19		T2	16		T3	2
zero	8485	1			T1	94		T2	64		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	490	1			T1	7		T2	2		T23	1
uni	3586	1			T1	48		T2	29		T8	1
gen	3916	1			T1	40		T2	26		T3	2
res	823	1			T1	6		T2	7		T3	2
ins	4099	1			T1	48		T2	29		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8740

1

T1

112

T2

68

T3

5

mubi_true

4174

1

T1

37

T2

25

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

26

1

T32

1

T59

1

T57

1

pass

12888

1

T1

149

T2

93

T3

6

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	110	1			T1	2		T23	1		T4	1
upd	non_zero_bins[0]	pass	mubi_true	123	1			T1	1		T4	3		T82	1
upd	non_zero_bins[1]	pass	mubi_false	78	1			T1	2		T2	1		T83	1
upd	non_zero_bins[1]	pass	mubi_true	86	1			T1	1		T2	1		T45	1
upd	zero	pass	mubi_false	54	1			T4	1		T82	1		T164	1
upd	zero	pass	mubi_true	39	1			T1	1		T24	1		T45	1
uni	zero	fail	mubi_false	4	1			T32	1		T190	1		T244	1
uni	zero	pass	mubi_false	2608	1			T1	38		T2	22		T8	1
uni	zero	pass	mubi_true	974	1			T1	10		T2	7		T4	4
gen	non_zero_bins[0]	pass	mubi_false	448	1			T1	8		T2	3		T8	4
gen	non_zero_bins[0]	pass	mubi_true	531	1			T1	2		T2	3		T4	2
gen	non_zero_bins[1]	pass	mubi_false	358	1			T1	4		T2	2		T3	2
gen	non_zero_bins[1]	pass	mubi_true	314	1			T1	3		T2	3		T23	1
gen	zero	fail	mubi_false	13	1			T59	1		T92	1		T93	1
gen	zero	pass	mubi_false	1850	1			T1	22		T2	14		T4	8
gen	zero	pass	mubi_true	402	1			T1	1		T2	1		T23	1
res	non_zero_bins[0]	pass	mubi_false	197	1			T1	1		T2	2		T3	2
res	non_zero_bins[0]	pass	mubi_true	184	1			T1	2		T2	1		T8	2
res	non_zero_bins[1]	pass	mubi_false	134	1			T2	1		T4	1		T25	1
res	non_zero_bins[1]	pass	mubi_true	112	1			T1	1		T2	1		T9	1
res	zero	fail	mubi_false	5	1			T57	1		T188	1		T245	1
res	zero	pass	mubi_false	91	1			T1	1		T47	2		T6	1
res	zero	pass	mubi_true	100	1			T1	1		T2	2		T67	1
ins	non_zero_bins[0]	pass	mubi_false	512	1			T1	11		T2	3		T4	2
ins	non_zero_bins[0]	pass	mubi_true	508	1			T1	9		T2	1		T3	1
ins	non_zero_bins[1]	pass	mubi_false	356	1			T1	4		T2	4		T26	2
ins	non_zero_bins[1]	pass	mubi_true	378	1			T1	4		T2	3		T24	1
ins	zero	fail	mubi_false	3	1			T78	1		T143	1		T246	1
ins	zero	fail	mubi_true	1	1			T247	1		-	-		-	-
ins	zero	pass	mubi_false	1919	1			T1	19		T2	16		T3	1
ins	zero	pass	mubi_true	422	1			T1	1		T2	2		T8	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded