Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T8
DataWait	75	Covered	T1,T2,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T157,T158,T169
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T8
DataWait->AckPls	80	Covered	T1,T2,T8
DataWait->Disabled	107	Covered	T47,T21,T94
DataWait->Error	99	Covered	T41,T73,T141
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T8
Idle	-	1	0	-	Covered	T1,T2,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T8
DataWait	-	-	-	0	Covered	T1,T2,T8
AckPls	-	-	-	-	Covered	T1,T2,T8
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T84,T127,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1553612984	991541	0	0
FpvSecCmErrorStEscalate_A	1553612984	998814	0	0
u_state_regs_A	1553582564	1552391080	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1553612984	991541	0	0
T5	16240	7952	0	0
T6	0	2534	0	0
T7	0	4466	0	0
T13	0	4298	0	0
T14	0	3983	0	0
T18	19138	0	0	0
T32	16233	0	0	0
T40	4606	1491	0	0
T41	0	6440	0	0
T45	713776	0	0	0
T46	7119	0	0	0
T60	13251	0	0	0
T61	9506	0	0	0
T80	7588	0	0	0
T84	0	2225	0	0
T85	9849	0	0	0
T127	0	7440	0	0
T161	0	7686	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1553612984	998814	0	0
T5	16240	7959	0	0
T6	0	2541	0	0
T7	0	4473	0	0
T13	0	4305	0	0
T14	0	3990	0	0
T18	19138	0	0	0
T32	16233	0	0	0
T40	4606	1498	0	0
T41	0	6447	0	0
T45	713776	0	0	0
T46	7119	0	0	0
T60	13251	0	0	0
T61	9506	0	0	0
T80	7588	0	0	0
T84	0	2232	0	0
T85	9849	0	0	0
T127	0	7447	0	0
T161	0	7693	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1553582564	1552391080	0	0
T1	4773034	4772467	0	0
T2	1535065	1535002	0	0
T3	12439	11802	0	0
T4	154385	150752	0	0
T8	8729	8064	0	0
T22	5852	5320	0	0
T23	7742	7098	0	0
T24	29407	28959	0	0
T25	15645	15141	0	0
T26	33012	32536	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T8
DataWait	75	Covered	T1,T2,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T8
DataWait->AckPls	80	Covered	T1,T2,T8
DataWait->Disabled	107	Covered	T171,T172
DataWait->Error	99	Covered	T141,T137,T134
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T8
Idle	-	1	0	-	Covered	T1,T2,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T8
DataWait	-	-	-	0	Covered	T1,T2,T8
AckPls	-	-	-	-	Covered	T1,T2,T8
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T84,T127,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	139763	0	0
FpvSecCmErrorStEscalate_A	221944712	140802	0	0
u_state_regs_A	221914292	221744080	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	139763	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	275	0	0
T85	1407	0	0	0
T127	0	1020	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	140802	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	276	0	0
T85	1407	0	0	0
T127	0	1021	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221914292	221744080	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T10,T50
DataWait	75	Covered	T23,T41,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T23,T10,T50
DataWait->AckPls	80	Covered	T23,T10,T50
DataWait->Disabled	107	Covered	T173,T174,T175
DataWait->Error	99	Covered	T41,T73,T63
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T41,T10
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T84,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T10,T50
Idle	-	1	0	-	Covered	T23,T41,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T10,T50
DataWait	-	-	-	0	Covered	T23,T41,T10
AckPls	-	-	-	-	Covered	T23,T10,T50
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T30,T47
DataWait	75	Covered	T25,T30,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T30,T47
DataWait->AckPls	80	Covered	T25,T30,T47
DataWait->Disabled	107	Covered	T94,T176,T177
DataWait->Error	99	Covered	T178,T179,T180
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T30,T47
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T30,T47
Idle	-	1	0	-	Covered	T25,T30,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T30,T47
DataWait	-	-	-	0	Covered	T25,T30,T47
AckPls	-	-	-	-	Covered	T25,T30,T47
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T47,T48
DataWait	75	Covered	T25,T47,T48
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T47,T48
DataWait->AckPls	80	Covered	T25,T47,T48
DataWait->Disabled	107	Covered	T47,T98,T125
DataWait->Error	99	Covered	T130,T181,T182
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T47,T48
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T47,T48
Idle	-	1	0	-	Covered	T25,T47,T48
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T47,T48
DataWait	-	-	-	0	Covered	T25,T47,T48
AckPls	-	-	-	-	Covered	T25,T47,T48
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T38,T11
DataWait	75	Covered	T25,T38,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T38,T11
DataWait->AckPls	80	Covered	T25,T38,T11
DataWait->Disabled	107	Covered	T101,T126
DataWait->Error	99	Covered	T183,T136
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T38,T11
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T38,T11
Idle	-	1	0	-	Covered	T25,T38,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T38,T11
DataWait	-	-	-	0	Covered	T25,T11,T58
AckPls	-	-	-	-	Covered	T25,T38,T11
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T23,T18
DataWait	75	Covered	T8,T23,T18
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T157,T169
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T23,T18
DataWait->AckPls	80	Covered	T8,T23,T18
DataWait->Disabled	107	Covered	T86,T184,T185
DataWait->Error	99	Covered	T123,T145,T186
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T23,T18
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T23,T18
Idle	-	1	0	-	Covered	T8,T23,T18
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T23,T18
DataWait	-	-	-	0	Covered	T8,T23,T18
AckPls	-	-	-	-	Covered	T8,T23,T18
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T46

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T25,T46
DataWait	75	Covered	T3,T25,T46
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T40,T5,T41
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T158
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T25,T46
DataWait->AckPls	80	Covered	T3,T25,T46
DataWait->Disabled	107	Covered	T21,T124,T147
DataWait->Error	99	Covered	T114,T65,T187
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T89,T67,T170
EndPointClear->Error	99	Covered	T5,T7,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T25,T46
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T40,T41,T84

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T25,T46
Idle	-	1	0	-	Covered	T3,T25,T46
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T25,T46
DataWait	-	-	-	0	Covered	T3,T25,T46
AckPls	-	-	-	-	Covered	T3,T25,T46
Error	-	-	-	-	Covered	T40,T5,T41
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T40,T5,T41
0	1	Covered	T3,T9,T46
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	221944712	141963	0	0
FpvSecCmErrorStEscalate_A	221944712	143002	0	0
u_state_regs_A	221944712	221774500	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	141963	0	0
T5	2320	1136	0	0
T6	0	362	0	0
T7	0	638	0	0
T13	0	614	0	0
T14	0	569	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	213	0	0
T41	0	920	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	325	0	0
T85	1407	0	0	0
T127	0	1070	0	0
T161	0	1098	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	143002	0	0
T5	2320	1137	0	0
T6	0	363	0	0
T7	0	639	0	0
T13	0	615	0	0
T14	0	570	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T40	658	214	0	0
T41	0	921	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	326	0	0
T85	1407	0	0	0
T127	0	1071	0	0
T161	0	1099	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0