Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T39,T42,T104
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T43,T44
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	443214906	1904764	0	0
DepthKnown_A	443889424	443549000	0	0
RvalidKnown_A	443889424	443549000	0	0
WreadyKnown_A	443889424	443549000	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	443555776	1975420	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443214906	1904764	0	0
T3	3554	2528	0	0
T4	44110	0	0	0
T5	0	227	0	0
T6	0	91	0	0
T7	0	230	0	0
T8	2494	515	0	0
T9	0	2956	0	0
T18	0	3878	0	0
T19	0	2158	0	0
T21	0	3802	0	0
T22	1672	0	0	0
T23	2212	0	0	0
T24	8402	0	0	0
T25	4470	0	0	0
T26	9432	0	0	0
T30	1312	0	0	0
T47	0	2733	0	0
T81	3148	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443889424	443549000	0	0
T1	1363724	1363562	0	0
T2	438590	438572	0	0
T3	3554	3372	0	0
T4	44110	43072	0	0
T8	2494	2304	0	0
T22	1672	1520	0	0
T23	2212	2028	0	0
T24	8402	8274	0	0
T25	4470	4326	0	0
T26	9432	9296	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443889424	443549000	0	0
T1	1363724	1363562	0	0
T2	438590	438572	0	0
T3	3554	3372	0	0
T4	44110	43072	0	0
T8	2494	2304	0	0
T22	1672	1520	0	0
T23	2212	2028	0	0
T24	8402	8274	0	0
T25	4470	4326	0	0
T26	9432	9296	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	443889424	443549000	0	0
T1	1363724	1363562	0	0
T2	438590	438572	0	0
T3	3554	3372	0	0
T4	44110	43072	0	0
T8	2494	2304	0	0
T22	1672	1520	0	0
T23	2212	2028	0	0
T24	8402	8274	0	0
T25	4470	4326	0	0
T26	9432	9296	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	443555776	1975420	0	0
T3	3554	2528	0	0
T4	44110	0	0	0
T5	0	1682	0	0
T6	0	793	0	0
T8	2494	515	0	0
T9	0	2956	0	0
T18	0	3878	0	0
T21	0	3802	0	0
T22	1672	0	0	0
T23	2212	0	0	0
T24	8402	0	0	0
T25	4470	0	0	0
T26	9432	0	0	0
T30	1312	0	0	0
T41	0	2218	0	0
T47	0	2733	0	0
T81	3148	0	0	0
T84	0	265	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T105
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T43,T106,T107
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	221607453	947328	0	0
DepthKnown_A	221944712	221774500	0	0
RvalidKnown_A	221944712	221774500	0	0
WreadyKnown_A	221944712	221774500	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221777888	982559	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221607453	947328	0	0
T3	1777	1250	0	0
T4	22055	0	0	0
T5	0	110	0	0
T6	0	39	0	0
T7	0	70	0	0
T8	1247	248	0	0
T9	0	1413	0	0
T18	0	1898	0	0
T19	0	1075	0	0
T21	0	1883	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T47	0	1351	0	0
T81	1574	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221777888	982559	0	0
T3	1777	1250	0	0
T4	22055	0	0	0
T5	0	819	0	0
T6	0	381	0	0
T8	1247	248	0	0
T9	0	1413	0	0
T18	0	1898	0	0
T21	0	1883	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T41	0	1110	0	0
T47	0	1351	0	0
T81	1574	0	0	0
T84	0	137	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T39,T42,T104
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T44,T108
1	0	1	Covered	T3,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	221607453	957436	0	0
DepthKnown_A	221944712	221774500	0	0
RvalidKnown_A	221944712	221774500	0	0
WreadyKnown_A	221944712	221774500	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	221777888	992861	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221607453	957436	0	0
T3	1777	1278	0	0
T4	22055	0	0	0
T5	0	117	0	0
T6	0	52	0	0
T7	0	160	0	0
T8	1247	267	0	0
T9	0	1543	0	0
T18	0	1980	0	0
T19	0	1083	0	0
T21	0	1919	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T47	0	1382	0	0
T81	1574	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	221777888	992861	0	0
T3	1777	1278	0	0
T4	22055	0	0	0
T5	0	863	0	0
T6	0	412	0	0
T8	1247	267	0	0
T9	0	1543	0	0
T18	0	1980	0	0
T21	0	1919	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T41	0	1108	0	0
T47	0	1382	0	0
T81	1574	0	0	0
T84	0	128	0	0