Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	565585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4311830

1

T1

22

T2

6

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1309891	1			T1	36		T2	1		T3	55
values[0x0]	1648375	1			T1	11		T2	9		T3	10
values[0x1]	1919149	1			T1	12		T2	17		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	286109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4591306

1

T1

32

T2

10

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18869	1			T3	3		T4	4		T40	132
valid_sources[0x01]	18538	1			T4	6		T26	1		T11	1
valid_sources[0x02]	19280	1			T3	1		T4	2		T25	1
valid_sources[0x03]	18873	1			T4	7		T5	1		T64	3
valid_sources[0x04]	18752	1			T2	1		T4	2		T25	5
valid_sources[0x05]	17987	1			T1	1		T5	1		T40	133
valid_sources[0x06]	18801	1			T1	1		T11	1		T40	134
valid_sources[0x07]	18886	1			T4	3		T5	1		T40	127
valid_sources[0x08]	18850	1			T1	1		T3	1		T4	3
valid_sources[0x09]	18602	1			T4	1		T40	141		T55	2
valid_sources[0x0a]	18774	1			T4	8		T11	3		T12	22
valid_sources[0x0b]	18377	1			T4	4		T11	5		T64	4
valid_sources[0x0c]	19800	1			T40	116		T55	4		T43	2
valid_sources[0x0d]	19465	1			T3	1		T4	6		T64	1
valid_sources[0x0e]	19057	1			T4	7		T64	1		T40	133
valid_sources[0x0f]	19033	1			T5	1		T40	134		T164	2
valid_sources[0x10]	19739	1			T3	1		T4	4		T40	131
valid_sources[0x11]	19542	1			T4	2		T40	131		T55	1
valid_sources[0x12]	19257	1			T4	1		T11	2		T40	129
valid_sources[0x13]	19582	1			T40	143		T23	1		T43	1
valid_sources[0x14]	18369	1			T4	1		T26	1		T40	134
valid_sources[0x15]	20468	1			T1	1		T4	3		T40	149
valid_sources[0x16]	18510	1			T4	1		T26	1		T11	7
valid_sources[0x17]	19453	1			T1	1		T4	1		T11	5
valid_sources[0x18]	19490	1			T4	1		T5	1		T40	140
valid_sources[0x19]	18818	1			T4	5		T25	1		T40	137
valid_sources[0x1a]	18602	1			T3	1		T10	92		T40	136
valid_sources[0x1b]	18503	1			T4	3		T40	144		T55	1
valid_sources[0x1c]	19264	1			T2	1		T3	1		T4	1
valid_sources[0x1d]	19201	1			T40	125		T55	2		T43	2
valid_sources[0x1e]	18365	1			T1	1		T4	6		T40	132
valid_sources[0x1f]	19139	1			T4	3		T11	5		T5	1
valid_sources[0x20]	19855	1			T1	1		T4	5		T25	1
valid_sources[0x21]	19442	1			T3	2		T4	2		T11	2
valid_sources[0x22]	18174	1			T4	3		T25	1		T64	3
valid_sources[0x23]	19066	1			T1	1		T4	2		T53	3
valid_sources[0x24]	18640	1			T3	1		T4	3		T64	2
valid_sources[0x25]	18603	1			T4	1		T40	128		T55	1
valid_sources[0x26]	18716	1			T3	2		T4	1		T40	135
valid_sources[0x27]	18311	1			T4	8		T64	2		T40	121
valid_sources[0x28]	18169	1			T3	2		T4	3		T12	3
valid_sources[0x29]	17716	1			T4	4		T6	1		T40	142
valid_sources[0x2a]	19025	1			T1	1		T3	2		T4	3
valid_sources[0x2b]	18965	1			T3	1		T4	3		T40	134
valid_sources[0x2c]	19118	1			T11	7		T36	2		T64	3
valid_sources[0x2d]	18786	1			T1	1		T4	6		T40	160
valid_sources[0x2e]	18419	1			T4	1		T11	1		T64	2
valid_sources[0x2f]	19371	1			T3	4		T4	1		T11	1
valid_sources[0x30]	19544	1			T1	1		T4	1		T11	1
valid_sources[0x31]	18496	1			T26	1		T40	123		T55	3
valid_sources[0x32]	18187	1			T1	1		T4	1		T25	1
valid_sources[0x33]	18468	1			T25	1		T40	124		T55	3
valid_sources[0x34]	18743	1			T2	1		T4	3		T25	2
valid_sources[0x35]	19019	1			T2	1		T11	5		T40	141
valid_sources[0x36]	20238	1			T4	3		T64	1		T40	143
valid_sources[0x37]	18966	1			T1	1		T4	1		T25	5
valid_sources[0x38]	19119	1			T3	1		T4	3		T40	118
valid_sources[0x39]	20288	1			T3	1		T4	1		T12	6
valid_sources[0x3a]	18131	1			T40	125		T55	2		T23	1
valid_sources[0x3b]	18450	1			T4	6		T40	135		T23	2
valid_sources[0x3c]	19610	1			T4	1		T40	130		T55	4
valid_sources[0x3d]	19699	1			T4	2		T53	3		T40	120
valid_sources[0x3e]	17600	1			T1	1		T4	3		T53	6
valid_sources[0x3f]	19864	1			T3	1		T4	4		T64	1
valid_sources[0x40]	18239	1			T1	1		T4	1		T25	3
valid_sources[0x41]	19458	1			T3	1		T4	1		T63	1
valid_sources[0x42]	19052	1			T1	2		T2	1		T4	1
valid_sources[0x43]	19493	1			T4	6		T5	1		T40	152
valid_sources[0x44]	18181	1			T4	2		T25	1		T64	3
valid_sources[0x45]	18547	1			T4	8		T5	1		T40	136
valid_sources[0x46]	17698	1			T4	5		T11	5		T63	1
valid_sources[0x47]	18984	1			T63	2		T40	143		T55	2
valid_sources[0x48]	18897	1			T4	1		T40	122		T55	2
valid_sources[0x49]	18946	1			T1	3		T2	1		T3	1
valid_sources[0x4a]	18355	1			T4	2		T64	2		T40	123
valid_sources[0x4b]	18873	1			T4	1		T11	3		T6	1
valid_sources[0x4c]	19301	1			T3	1		T4	1		T11	3
valid_sources[0x4d]	18930	1			T1	1		T4	1		T11	4
valid_sources[0x4e]	19210	1			T3	1		T4	3		T64	1
valid_sources[0x4f]	18047	1			T2	1		T40	123		T55	3
valid_sources[0x50]	18942	1			T36	4		T64	1		T40	137
valid_sources[0x51]	19475	1			T4	5		T6	1		T40	125
valid_sources[0x52]	18871	1			T1	4		T4	3		T53	3
valid_sources[0x53]	18764	1			T1	1		T2	1		T11	1
valid_sources[0x54]	19394	1			T4	1		T40	129		T160	2
valid_sources[0x55]	18977	1			T2	1		T4	1		T11	3
valid_sources[0x56]	18748	1			T40	117		T55	1		T23	1
valid_sources[0x57]	19259	1			T3	1		T4	6		T40	135
valid_sources[0x58]	18037	1			T3	1		T4	1		T40	140
valid_sources[0x59]	18720	1			T4	1		T11	1		T64	1
valid_sources[0x5a]	18436	1			T1	1		T4	3		T40	126
valid_sources[0x5b]	22439	1			T11	2		T40	127		T43	1
valid_sources[0x5c]	19952	1			T4	2		T25	2		T11	1
valid_sources[0x5d]	18910	1			T4	4		T40	125		T55	3
valid_sources[0x5e]	17560	1			T4	5		T25	1		T40	132
valid_sources[0x5f]	18020	1			T64	1		T40	137		T33	3
valid_sources[0x60]	20128	1			T40	126		T43	1		T160	1
valid_sources[0x61]	18816	1			T4	3		T64	3		T40	113
valid_sources[0x62]	19672	1			T4	1		T64	1		T40	117
valid_sources[0x63]	19117	1			T4	2		T25	4		T40	135
valid_sources[0x64]	19743	1			T4	1		T25	2		T11	4
valid_sources[0x65]	19726	1			T25	1		T40	134		T33	2
valid_sources[0x66]	18670	1			T1	1		T2	1		T3	1
valid_sources[0x67]	19710	1			T4	1		T40	121		T23	1
valid_sources[0x68]	17763	1			T4	1		T40	133		T160	1
valid_sources[0x69]	19925	1			T3	1		T40	144		T23	2
valid_sources[0x6a]	18433	1			T4	4		T62	228		T40	129
valid_sources[0x6b]	18454	1			T25	1		T40	131		T55	2
valid_sources[0x6c]	17754	1			T4	2		T40	144		T160	6
valid_sources[0x6d]	20589	1			T4	2		T40	124		T23	3
valid_sources[0x6e]	19580	1			T4	1		T40	152		T23	2
valid_sources[0x6f]	18934	1			T2	1		T4	3		T40	134
valid_sources[0x70]	18911	1			T40	94		T76	18		T160	3
valid_sources[0x71]	18399	1			T4	5		T25	9		T64	2
valid_sources[0x72]	19230	1			T4	2		T25	2		T40	119
valid_sources[0x73]	18775	1			T3	4		T4	4		T40	130
valid_sources[0x74]	18059	1			T4	4		T25	3		T63	3
valid_sources[0x75]	18208	1			T2	2		T64	1		T40	138
valid_sources[0x76]	18885	1			T1	1		T2	1		T4	4
valid_sources[0x77]	18656	1			T4	3		T53	5		T40	137
valid_sources[0x78]	18800	1			T1	1		T3	1		T4	1
valid_sources[0x79]	20839	1			T3	4		T26	1		T40	123
valid_sources[0x7a]	19225	1			T4	1		T63	3		T40	113
valid_sources[0x7b]	18805	1			T1	1		T2	1		T4	2
valid_sources[0x7c]	19738	1			T1	1		T4	2		T11	3
valid_sources[0x7d]	17997	1			T4	1		T11	7		T40	146
valid_sources[0x7e]	18303	1			T40	116		T23	1		T160	4
valid_sources[0x7f]	18637	1			T4	2		T40	114		T43	2
valid_sources[0x80]	19782	1			T4	3		T11	4		T64	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1087471

1

T1

4

T2

1

T3

9

values[0x0]

all_enables

biggest_size

1612742

1

T1

10

T2

3

T3

5

values[0x1]

all_enables

biggest_size

1611617

1

T1

8

T2

2

T3

4