Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2422	1			T1	1		T4	6		T25	1
non_zero_bins[1]	1741	1			T1	1		T4	3		T25	1
zero	8081	1			T1	5		T3	6		T4	26

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	447	1			T1	1		T4	2		T25	1
uni	3413	1			T1	2		T3	1		T4	11
gen	3682	1			T1	2		T3	3		T4	10
res	799	1			T4	1		T10	1		T11	2
ins	3903	1			T1	2		T3	2		T4	11

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8340

1

T1

5

T3

3

T4

25

mubi_true

3904

1

T1

2

T3

3

T4

10

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

25

1

T22

1

T30

1

T54

1

pass

12219

1

T1

7

T3

6

T4

35

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	102	1			T4	1		T164	2		T41	1
upd	non_zero_bins[0]	pass	mubi_true	97	1			T40	2		T160	2		T41	2
upd	non_zero_bins[1]	pass	mubi_false	81	1			T4	1		T25	1		T55	1
upd	non_zero_bins[1]	pass	mubi_true	69	1			T41	2		T196	1		T197	1
upd	zero	pass	mubi_false	52	1			T1	1		T40	1		T42	1
upd	zero	pass	mubi_true	46	1			T41	1		T255	1		T197	1
uni	zero	fail	mubi_false	4	1			T22	1		T54	1		T256	1
uni	zero	pass	mubi_false	2486	1			T1	2		T3	1		T4	8
uni	zero	pass	mubi_true	923	1			T4	3		T62	2		T63	1
gen	non_zero_bins[0]	pass	mubi_false	445	1			T4	1		T11	3		T40	3
gen	non_zero_bins[0]	pass	mubi_true	427	1			T4	2		T40	1		T23	3
gen	non_zero_bins[1]	pass	mubi_false	315	1			T10	1		T12	1		T64	1
gen	non_zero_bins[1]	pass	mubi_true	367	1			T1	1		T21	2		T53	2
gen	zero	fail	mubi_false	15	1			T105	1		T169	1		T257	1
gen	zero	pass	mubi_false	1744	1			T3	1		T4	7		T12	11
gen	zero	pass	mubi_true	369	1			T1	1		T3	2		T25	2
res	non_zero_bins[0]	pass	mubi_false	173	1			T11	2		T53	2		T41	2
res	non_zero_bins[0]	pass	mubi_true	180	1			T10	1		T12	2		T21	2
res	non_zero_bins[1]	pass	mubi_false	122	1			T23	2		T24	3		T164	1
res	non_zero_bins[1]	pass	mubi_true	111	1			T64	1		T48	2		T41	1
res	zero	fail	mubi_false	3	1			T167	1		T192	1		T258	1
res	zero	pass	mubi_false	111	1			T44	3		T40	1		T24	1
res	zero	pass	mubi_true	99	1			T4	1		T166	2		T163	1
ins	non_zero_bins[0]	pass	mubi_false	526	1			T1	1		T4	1		T25	1
ins	non_zero_bins[0]	pass	mubi_true	472	1			T4	1		T10	1		T44	1
ins	non_zero_bins[1]	pass	mubi_false	342	1			T40	2		T23	1		T160	1
ins	non_zero_bins[1]	pass	mubi_true	334	1			T4	2		T12	1		T21	1
ins	zero	fail	mubi_false	2	1			T30	1		T143	1		-	-
ins	zero	fail	mubi_true	1	1			T259	1		-	-		-	-
ins	zero	pass	mubi_false	1817	1			T1	1		T3	1		T4	6
ins	zero	pass	mubi_true	409	1			T3	1		T4	1		T26	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded