Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T4
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T26,T153,T154
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T4
DataWait->AckPls	80	Covered	T1,T3,T4
DataWait->Disabled	107	Covered	T24,T134,T135
DataWait->Error	99	Covered	T82,T56,T7
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T3,T4
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T3,T4
DataWait	-	-	-	0	Covered	T1,T4,T25
AckPls	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T5,T36,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1178703960	1015727	0	0
FpvSecCmErrorStEscalate_A	1178703960	1022993	0	0
u_state_regs_A	1178668706	1177496955	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1178703960	1015727	0	0
T5	11340	6600	0	0
T6	7441	4284	0	0
T16	0	4466	0	0
T17	0	2464	0	0
T36	5957	2001	0	0
T40	1023435	0	0	0
T44	21357	0	0	0
T53	36757	0	0	0
T55	59395	0	0	0
T56	0	7966	0	0
T62	39088	0	0	0
T63	9492	0	0	0
T64	15911	0	0	0
T80	0	7748	0	0
T81	0	1750	0	0
T82	0	6530	0	0
T83	0	4340	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1178703960	1022993	0	0
T5	11340	6607	0	0
T6	7441	4291	0	0
T16	0	4473	0	0
T17	0	2471	0	0
T36	5957	2008	0	0
T40	1023435	0	0	0
T44	21357	0	0	0
T53	36757	0	0	0
T55	59395	0	0	0
T56	0	7973	0	0
T62	39088	0	0	0
T63	9492	0	0	0
T64	15911	0	0	0
T80	0	7755	0	0
T81	0	1757	0	0
T82	0	6537	0	0
T83	0	4347	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1178668706	1177496955	0	0
T1	15946	15407	0	0
T2	7441	6748	0	0
T3	13426	12992	0	0
T4	111881	108493	0	0
T10	46158	45479	0	0
T11	20447	19866	0	0
T12	16947	16597	0	0
T21	25025	24423	0	0
T25	19544	18928	0	0
T26	7357	6811	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T11,T36
DataWait	75	Covered	T25,T11,T36
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T11,T36
DataWait->AckPls	80	Covered	T25,T11,T36
DataWait->Disabled	107	Covered	T134,T173,T110
DataWait->Error	99	Covered	T9,T174,T175
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T25,T11,T36
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T25,T11,T36
Idle	-	1	0	-	Covered	T25,T11,T36
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T25,T11,T36
DataWait	-	-	-	0	Covered	T25,T11,T45
AckPls	-	-	-	-	Covered	T25,T11,T36
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T25,T11
DataWait	75	Covered	T3,T25,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T25,T11
DataWait->AckPls	80	Covered	T3,T25,T11
DataWait->Disabled	107	Covered	T135,T176,T177
DataWait->Error	99	Covered	T82,T59,T132
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T25,T11
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T25,T11
Idle	-	1	0	-	Covered	T3,T25,T11
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T25,T11
DataWait	-	-	-	0	Covered	T25,T11,T21
AckPls	-	-	-	-	Covered	T3,T25,T11
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T11,T24
DataWait	75	Covered	T25,T11,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T11,T24
DataWait->AckPls	80	Covered	T25,T11,T24
DataWait->Disabled	107	Covered	T123
DataWait->Error	99	Covered	T61,T178,T107
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T25,T11,T24
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T25,T11,T24
Idle	-	1	0	-	Covered	T25,T11,T24
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T25,T11,T24
DataWait	-	-	-	0	Covered	T25,T11,T24
AckPls	-	-	-	-	Covered	T25,T11,T24
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T25,T43
DataWait	75	Covered	T3,T25,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T25,T43
DataWait->AckPls	80	Covered	T3,T25,T43
DataWait->Disabled	107	Covered	T108,T179,T180
DataWait->Error	99	Covered	T181
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T25,T43
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T25,T43
Idle	-	1	0	-	Covered	T3,T25,T43
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T25,T43
DataWait	-	-	-	0	Covered	T3,T25,T43
AckPls	-	-	-	-	Covered	T3,T25,T43
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T44,T24
DataWait	75	Covered	T25,T44,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T44,T24
DataWait->AckPls	80	Covered	T25,T44,T24
DataWait->Disabled	107	Covered	T24,T136,T122
DataWait->Error	99	Covered	T17,T182
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T25,T44,T24
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T25,T44,T24
Idle	-	1	0	-	Covered	T25,T44,T24
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T25,T44,T24
DataWait	-	-	-	0	Covered	T25,T44,T24
AckPls	-	-	-	-	Covered	T25,T44,T24
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T4,T25
DataWait	75	Covered	T1,T4,T25
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T26,T154,T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T4,T25
DataWait->AckPls	80	Covered	T1,T4,T25
DataWait->Disabled	107	Covered	T184,T109,T147
DataWait->Error	99	Covered	T56,T7,T57
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T60,T18
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T4,T25
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T6,T81,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T4,T25
Idle	-	1	0	-	Covered	T1,T4,T25
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T4,T25
DataWait	-	-	-	0	Covered	T1,T4,T25
AckPls	-	-	-	-	Covered	T1,T4,T25
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T5,T36,T80

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	143561	0	0
FpvSecCmErrorStEscalate_A	168386280	144599	0	0
u_state_regs_A	168351026	168183633	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	143561	0	0
T5	1620	900	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	243	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1064	0	0
T81	0	250	0	0
T82	0	890	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	144599	0	0
T5	1620	901	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	244	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1065	0	0
T81	0	251	0	0
T82	0	891	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168351026	168183633	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T21,T53
DataWait	75	Covered	T25,T21,T53
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T36
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T153,T185
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T21,T53
DataWait->AckPls	80	Covered	T25,T21,T53
DataWait->Disabled	107	Covered	T186,T187
DataWait->Error	99	Covered	T81,T188
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T97,T172,T151
EndPointClear->Error	99	Covered	T155,T8,T60
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T25,T21,T53
Idle->Disabled	107	Covered	T3,T4,T26
Idle->Error	99	Covered	T5,T6,T36

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T25,T21,T53
Idle	-	1	0	-	Covered	T25,T21,T6
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T25,T21,T53
DataWait	-	-	-	0	Covered	T25,T21,T53
AckPls	-	-	-	-	Covered	T25,T21,T53
Error	-	-	-	-	Covered	T5,T6,T36
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T36
0	1	Covered	T3,T26,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	168386280	145361	0	0
FpvSecCmErrorStEscalate_A	168386280	146399	0	0
u_state_regs_A	168386280	168218887	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	145361	0	0
T5	1620	950	0	0
T6	1063	612	0	0
T16	0	638	0	0
T17	0	352	0	0
T36	851	293	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1138	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1114	0	0
T81	0	250	0	0
T82	0	940	0	0
T83	0	620	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	146399	0	0
T5	1620	951	0	0
T6	1063	613	0	0
T16	0	639	0	0
T17	0	353	0	0
T36	851	294	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1139	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1115	0	0
T81	0	251	0	0
T82	0	941	0	0
T83	0	621	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0