Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T37,T32
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T38,T39
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336075434	531326	0	0
DepthKnown_A	336772560	336437774	0	0
RvalidKnown_A	336772560	336437774	0	0
WreadyKnown_A	336772560	336437774	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	336439804	607559	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336075434	531326	0	0
T5	184	0	0	0
T6	206	0	0	0
T10	13188	10580	0	0
T11	5842	2901	0	0
T12	4842	2153	0	0
T21	7150	3984	0	0
T22	0	543	0	0
T23	0	961	0	0
T24	0	4815	0	0
T36	654	0	0	0
T44	0	3252	0	0
T47	0	7739	0	0
T53	10502	6394	0	0
T62	11168	0	0	0
T63	2712	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336772560	336437774	0	0
T1	4556	4402	0	0
T2	2126	1928	0	0
T3	3836	3712	0	0
T4	31966	30998	0	0
T10	13188	12994	0	0
T11	5842	5676	0	0
T12	4842	4742	0	0
T21	7150	6978	0	0
T25	5584	5408	0	0
T26	2102	1946	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336772560	336437774	0	0
T1	4556	4402	0	0
T2	2126	1928	0	0
T3	3836	3712	0	0
T4	31966	30998	0	0
T10	13188	12994	0	0
T11	5842	5676	0	0
T12	4842	4742	0	0
T21	7150	6978	0	0
T25	5584	5408	0	0
T26	2102	1946	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	336772560	336437774	0	0
T1	4556	4402	0	0
T2	2126	1928	0	0
T3	3836	3712	0	0
T4	31966	30998	0	0
T10	13188	12994	0	0
T11	5842	5676	0	0
T12	4842	4742	0	0
T21	7150	6978	0	0
T25	5584	5408	0	0
T26	2102	1946	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	336439804	607559	0	0
T5	3240	294	0	0
T6	2126	220	0	0
T10	13188	10580	0	0
T11	5842	2901	0	0
T12	4842	2153	0	0
T21	7150	3984	0	0
T22	0	543	0	0
T23	0	961	0	0
T36	1702	0	0	0
T44	0	3252	0	0
T53	10502	6394	0	0
T62	11168	0	0	0
T63	2712	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T48,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T99,T100
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T39
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	168037717	261299	0	0
DepthKnown_A	168386280	168218887	0	0
RvalidKnown_A	168386280	168218887	0	0
WreadyKnown_A	168386280	168218887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	168219902	299517	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168037717	261299	0	0
T5	92	0	0	0
T6	103	0	0	0
T10	6594	5259	0	0
T11	2921	1439	0	0
T12	2421	1068	0	0
T21	3575	1939	0	0
T22	0	281	0	0
T23	0	479	0	0
T24	0	2392	0	0
T36	327	0	0	0
T44	0	1526	0	0
T47	0	3826	0	0
T53	5251	3170	0	0
T62	5584	0	0	0
T63	1356	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	168219902	299517	0	0
T5	1620	148	0	0
T6	1063	111	0	0
T10	6594	5259	0	0
T11	2921	1439	0	0
T12	2421	1068	0	0
T21	3575	1939	0	0
T22	0	281	0	0
T23	0	479	0	0
T36	851	0	0	0
T44	0	1526	0	0
T53	5251	3170	0	0
T62	5584	0	0	0
T63	1356	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T37
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T101,T102
1	0	1	Covered	T10,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	168037717	270027	0	0
DepthKnown_A	168386280	168218887	0	0
RvalidKnown_A	168386280	168218887	0	0
WreadyKnown_A	168386280	168218887	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	168219902	308042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168037717	270027	0	0
T5	92	0	0	0
T6	103	0	0	0
T10	6594	5321	0	0
T11	2921	1462	0	0
T12	2421	1085	0	0
T21	3575	2045	0	0
T22	0	262	0	0
T23	0	482	0	0
T24	0	2423	0	0
T36	327	0	0	0
T44	0	1726	0	0
T47	0	3913	0	0
T53	5251	3224	0	0
T62	5584	0	0	0
T63	1356	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	168219902	308042	0	0
T5	1620	146	0	0
T6	1063	109	0	0
T10	6594	5321	0	0
T11	2921	1462	0	0
T12	2421	1085	0	0
T21	3575	2045	0	0
T22	0	262	0	0
T23	0	482	0	0
T36	851	0	0	0
T44	0	1726	0	0
T53	5251	3224	0	0
T62	5584	0	0	0
T63	1356	0	0	0