Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T27	1		T28	1		T257	1
auto_req_mode	145	1			T9	1		T10	1		T11	1
sw_mode	2759	1			T3	1		T4	5		T22	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

299

1

T3

1

T9

1

T11

1

single

96

1

T10

1

T48

1

T257

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1120	1			T22	1		T10	1		T27	1
auto[2]	11	1			T11	1		T258	1		T68	1
auto[3]	121	1			T40	21		T70	1		T259	1
auto[4]	19	1			T21	1		T67	1		T260	1
auto[5]	90	1			T4	5		T261	8		T262	63
auto[6]	184	1			T66	1		T197	13		T184	28
auto[7]	1500	1			T3	1		T9	1		T5	7

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	81	1			T27	1		T28	1		T257	1
auto[1]	auto_req_mode	82	1			T10	1		T77	1		T144	1
auto[1]	sw_mode	957	1			T22	1		T51	14		T63	1
auto[2]	boot_req_mode	3	1			T263	1		T264	1		T265	1
auto[2]	auto_req_mode	3	1			T11	1		T258	1		T68	1
auto[2]	sw_mode	5	1			T266	1		T267	4		-	-
auto[3]	boot_req_mode	6	1			T268	1		T269	1		T270	1
auto[3]	auto_req_mode	6	1			T259	1		T271	1		T272	1
auto[3]	sw_mode	109	1			T40	21		T70	1		T273	1
auto[4]	boot_req_mode	2	1			T67	1		T260	1		-	-
auto[4]	auto_req_mode	3	1			T21	1		T274	1		T275	1
auto[4]	sw_mode	14	1			T276	1		T277	8		T278	1
auto[5]	boot_req_mode	2	1			T279	1		T280	1		-	-
auto[5]	auto_req_mode	7	1			T281	1		T282	1		T283	1
auto[5]	sw_mode	81	1			T4	5		T261	8		T262	63
auto[6]	boot_req_mode	6	1			T66	1		T284	1		T285	1
auto[6]	auto_req_mode	1	1			T286	1		-	-		-	-
auto[6]	sw_mode	177	1			T197	13		T184	28		T186	27
auto[7]	boot_req_mode	41	1			T72	1		T287	1		T240	1
auto[7]	auto_req_mode	43	1			T9	1		T20	1		T12	1
auto[7]	sw_mode	1416	1			T3	1		T5	7		T44	1