Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	681256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5573243

1

T1

9

T2

11

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1651492	1			T1	47		T2	1		T3	147
values[0x0]	2127936	1			T1	5		T2	20		T3	10
values[0x1]	2475071	1			T1	7		T2	19		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334409	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5920090

1

T1

22

T2

13

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23201	1			T20	1		T51	1		T40	372
valid_sources[0x01]	24276	1			T51	10		T40	461		T41	50
valid_sources[0x02]	22702	1			T1	1		T4	2		T20	1
valid_sources[0x03]	24779	1			T51	1		T63	1		T40	612
valid_sources[0x04]	25050	1			T1	2		T4	1		T9	1
valid_sources[0x05]	23861	1			T4	1		T9	3		T51	1
valid_sources[0x06]	22881	1			T1	1		T9	3		T51	2
valid_sources[0x07]	23717	1			T9	1		T51	2		T40	320
valid_sources[0x08]	24360	1			T3	1		T4	1		T10	1
valid_sources[0x09]	24504	1			T1	1		T9	3		T51	5
valid_sources[0x0a]	23761	1			T4	1		T10	1		T11	2
valid_sources[0x0b]	24330	1			T3	1		T20	1		T51	3
valid_sources[0x0c]	24083	1			T20	1		T51	7		T44	4
valid_sources[0x0d]	25469	1			T51	4		T40	442		T41	292
valid_sources[0x0e]	25204	1			T4	1		T9	1		T20	1
valid_sources[0x0f]	25056	1			T2	1		T3	3		T4	2
valid_sources[0x10]	23404	1			T4	4		T20	1		T40	328
valid_sources[0x11]	25332	1			T10	1		T51	10		T40	499
valid_sources[0x12]	24843	1			T1	1		T4	4		T9	2
valid_sources[0x13]	24275	1			T2	1		T44	2		T40	429
valid_sources[0x14]	25231	1			T3	1		T26	2		T40	515
valid_sources[0x15]	25315	1			T2	1		T20	2		T51	8
valid_sources[0x16]	24727	1			T4	1		T40	414		T41	599
valid_sources[0x17]	23679	1			T1	1		T51	1		T44	1
valid_sources[0x18]	24901	1			T4	3		T40	626		T15	7
valid_sources[0x19]	25788	1			T4	2		T9	2		T10	3
valid_sources[0x1a]	23922	1			T1	1		T2	1		T4	2
valid_sources[0x1b]	23338	1			T2	1		T3	2		T4	2
valid_sources[0x1c]	24206	1			T3	1		T4	4		T10	2
valid_sources[0x1d]	24699	1			T2	2		T3	1		T4	2
valid_sources[0x1e]	24407	1			T4	1		T20	1		T51	8
valid_sources[0x1f]	25308	1			T3	2		T9	4		T10	1
valid_sources[0x20]	24230	1			T1	1		T4	3		T9	2
valid_sources[0x21]	23855	1			T20	1		T51	1		T40	716
valid_sources[0x22]	24173	1			T4	3		T51	2		T63	1
valid_sources[0x23]	24339	1			T4	3		T9	2		T22	32
valid_sources[0x24]	24470	1			T3	1		T4	6		T51	1
valid_sources[0x25]	24484	1			T2	1		T9	2		T20	1
valid_sources[0x26]	23927	1			T9	1		T11	2		T20	1
valid_sources[0x27]	25811	1			T3	1		T4	2		T11	2
valid_sources[0x28]	24445	1			T2	1		T3	1		T4	4
valid_sources[0x29]	23686	1			T4	2		T11	3		T26	2
valid_sources[0x2a]	24143	1			T3	2		T20	1		T51	5
valid_sources[0x2b]	23936	1			T3	2		T11	3		T44	1
valid_sources[0x2c]	24029	1			T3	1		T20	1		T51	4
valid_sources[0x2d]	24247	1			T1	2		T40	443		T41	67
valid_sources[0x2e]	24595	1			T3	1		T4	1		T9	3
valid_sources[0x2f]	23634	1			T1	1		T10	2		T20	1
valid_sources[0x30]	24270	1			T2	1		T3	2		T10	1
valid_sources[0x31]	24208	1			T2	1		T9	2		T44	4
valid_sources[0x32]	24325	1			T3	1		T20	1		T51	1
valid_sources[0x33]	22916	1			T1	1		T3	1		T4	2
valid_sources[0x34]	24734	1			T1	1		T4	1		T10	1
valid_sources[0x35]	23776	1			T3	1		T4	1		T40	375
valid_sources[0x36]	24189	1			T3	4		T4	1		T22	5
valid_sources[0x37]	24449	1			T2	1		T4	3		T10	2
valid_sources[0x38]	22824	1			T3	1		T4	3		T11	2
valid_sources[0x39]	25461	1			T4	4		T22	1		T51	5
valid_sources[0x3a]	24746	1			T3	1		T9	1		T10	1
valid_sources[0x3b]	23612	1			T51	9		T40	359		T41	344
valid_sources[0x3c]	23904	1			T3	1		T9	1		T10	1
valid_sources[0x3d]	22886	1			T2	1		T22	9		T10	1
valid_sources[0x3e]	23971	1			T9	2		T11	4		T51	2
valid_sources[0x3f]	24574	1			T4	1		T51	4		T44	1
valid_sources[0x40]	23466	1			T4	1		T9	1		T20	1
valid_sources[0x41]	23468	1			T2	1		T4	1		T51	2
valid_sources[0x42]	24170	1			T11	2		T20	1		T51	4
valid_sources[0x43]	23815	1			T3	1		T4	3		T22	4
valid_sources[0x44]	23032	1			T1	1		T2	1		T20	1
valid_sources[0x45]	24325	1			T2	1		T4	2		T20	1
valid_sources[0x46]	22605	1			T2	1		T4	2		T20	2
valid_sources[0x47]	24465	1			T3	1		T10	1		T20	1
valid_sources[0x48]	23861	1			T3	1		T11	1		T20	1
valid_sources[0x49]	24465	1			T3	1		T4	1		T51	3
valid_sources[0x4a]	24160	1			T1	2		T26	1		T51	5
valid_sources[0x4b]	24883	1			T3	2		T4	2		T11	3
valid_sources[0x4c]	24133	1			T2	2		T4	2		T51	4
valid_sources[0x4d]	24806	1			T1	1		T3	5		T4	1
valid_sources[0x4e]	23822	1			T20	1		T51	3		T63	1
valid_sources[0x4f]	24226	1			T1	1		T4	1		T9	3
valid_sources[0x50]	24462	1			T9	2		T20	1		T51	4
valid_sources[0x51]	25149	1			T4	1		T51	1		T63	1
valid_sources[0x52]	26606	1			T4	1		T9	5		T26	9
valid_sources[0x53]	24805	1			T3	1		T4	3		T51	8
valid_sources[0x54]	25279	1			T10	1		T26	3		T51	2
valid_sources[0x55]	23446	1			T4	1		T10	1		T26	5
valid_sources[0x56]	24777	1			T40	456		T15	6		T41	27
valid_sources[0x57]	26847	1			T9	1		T10	1		T20	1
valid_sources[0x58]	24902	1			T3	2		T9	1		T20	1
valid_sources[0x59]	23533	1			T3	6		T4	1		T20	1
valid_sources[0x5a]	23829	1			T4	4		T51	8		T40	658
valid_sources[0x5b]	24656	1			T1	3		T4	1		T11	4
valid_sources[0x5c]	25061	1			T9	3		T10	1		T40	337
valid_sources[0x5d]	24538	1			T1	1		T3	1		T11	1
valid_sources[0x5e]	23765	1			T4	2		T51	3		T40	405
valid_sources[0x5f]	24466	1			T1	1		T9	1		T20	1
valid_sources[0x60]	23918	1			T1	1		T2	1		T11	1
valid_sources[0x61]	25077	1			T4	3		T9	1		T51	2
valid_sources[0x62]	23649	1			T4	2		T44	6		T40	490
valid_sources[0x63]	25387	1			T10	1		T20	1		T51	2
valid_sources[0x64]	23975	1			T2	1		T3	2		T10	1
valid_sources[0x65]	23248	1			T3	1		T4	2		T10	2
valid_sources[0x66]	24919	1			T2	1		T4	1		T9	1
valid_sources[0x67]	24096	1			T51	2		T44	1		T40	436
valid_sources[0x68]	25439	1			T20	1		T51	1		T44	1
valid_sources[0x69]	24220	1			T20	1		T51	2		T40	322
valid_sources[0x6a]	25447	1			T1	1		T4	3		T20	1
valid_sources[0x6b]	25401	1			T3	3		T4	2		T9	2
valid_sources[0x6c]	26170	1			T4	1		T10	1		T40	427
valid_sources[0x6d]	23427	1			T3	2		T4	3		T9	1
valid_sources[0x6e]	24793	1			T4	4		T44	1		T40	478
valid_sources[0x6f]	23852	1			T2	1		T3	3		T4	1
valid_sources[0x70]	23904	1			T44	3		T40	488		T15	7
valid_sources[0x71]	23795	1			T51	6		T63	3		T40	543
valid_sources[0x72]	23563	1			T3	3		T4	2		T22	11
valid_sources[0x73]	25005	1			T3	1		T10	1		T51	6
valid_sources[0x74]	25580	1			T10	1		T26	6		T51	2
valid_sources[0x75]	24103	1			T4	2		T44	2		T40	355
valid_sources[0x76]	23867	1			T4	1		T9	3		T10	1
valid_sources[0x77]	23856	1			T4	1		T40	498		T41	284
valid_sources[0x78]	24788	1			T3	1		T4	1		T10	3
valid_sources[0x79]	24657	1			T4	1		T10	3		T20	1
valid_sources[0x7a]	24699	1			T40	371		T41	378		T42	411
valid_sources[0x7b]	23784	1			T9	1		T10	2		T11	2
valid_sources[0x7c]	23672	1			T3	1		T4	2		T11	3
valid_sources[0x7d]	23391	1			T11	2		T20	2		T40	385
valid_sources[0x7e]	22843	1			T4	2		T44	3		T40	504
valid_sources[0x7f]	26013	1			T3	1		T4	1		T20	1
valid_sources[0x80]	23713	1			T4	1		T51	1		T63	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1405270

1

T1

3

T2

1

T3

6

values[0x0]

all_enables

biggest_size

2085186

1

T1

3

T2

5

T3

10

values[0x1]

all_enables

biggest_size

2082787

1

T1

3

T2

5

T3

10