Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2533	1			T4	4		T10	4		T11	2
non_zero_bins[1]	1836	1			T3	1		T4	1		T9	5
zero	8046	1			T1	2		T3	4		T4	14

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	488	1			T51	1		T40	4		T41	7
uni	3421	1			T3	2		T4	7		T22	1
gen	3804	1			T1	1		T3	1		T4	5
res	792	1			T9	2		T10	3		T11	2
ins	3910	1			T1	1		T3	2		T4	7

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8350

1

T1

2

T3

4

T4

12

mubi_true

4065

1

T3

1

T4

7

T9

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

21

1

T29

1

T30

1

T49

1

pass

12394

1

T1

2

T3

5

T4

19

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	112	1			T41	1		T42	2		T48	1
upd	non_zero_bins[0]	pass	mubi_true	119	1			T51	1		T40	2		T41	1
upd	non_zero_bins[1]	pass	mubi_false	76	1			T41	3		T142	1		T227	1
upd	non_zero_bins[1]	pass	mubi_true	93	1			T41	2		T42	2		T62	1
upd	zero	pass	mubi_false	43	1			T40	1		T42	1		T142	1
upd	zero	pass	mubi_true	45	1			T40	1		T42	2		T228	1
uni	zero	fail	mubi_false	9	1			T29	1		T139	1		T229	1
uni	zero	pass	mubi_false	2489	1			T3	2		T4	5		T5	2
uni	zero	pass	mubi_true	923	1			T4	2		T22	1		T5	5
gen	non_zero_bins[0]	pass	mubi_false	461	1			T51	1		T40	5		T21	3
gen	non_zero_bins[0]	pass	mubi_true	492	1			T4	1		T20	3		T51	1
gen	non_zero_bins[1]	pass	mubi_false	349	1			T9	2		T10	2		T11	2
gen	non_zero_bins[1]	pass	mubi_true	342	1			T63	1		T12	1		T40	2
gen	zero	fail	mubi_false	7	1			T49	1		T87	1		T147	1
gen	zero	pass	mubi_false	1752	1			T1	1		T3	1		T4	3
gen	zero	pass	mubi_true	401	1			T4	1		T20	1		T26	2
res	non_zero_bins[0]	pass	mubi_false	172	1			T10	3		T51	1		T12	2
res	non_zero_bins[0]	pass	mubi_true	161	1			T11	2		T40	2		T42	4
res	non_zero_bins[1]	pass	mubi_false	120	1			T63	1		T42	1		T62	1
res	non_zero_bins[1]	pass	mubi_true	150	1			T9	2		T20	2		T41	1
res	zero	fail	mubi_false	4	1			T148	1		T177	1		T179	1
res	zero	pass	mubi_false	92	1			T51	1		T41	1		T43	2
res	zero	pass	mubi_true	93	1			T40	1		T41	2		T72	1
ins	non_zero_bins[0]	pass	mubi_false	488	1			T10	1		T51	2		T12	1
ins	non_zero_bins[0]	pass	mubi_true	528	1			T4	3		T51	3		T40	2
ins	non_zero_bins[1]	pass	mubi_false	353	1			T3	1		T4	1		T11	1
ins	non_zero_bins[1]	pass	mubi_true	353	1			T9	1		T51	1		T40	3
ins	zero	fail	mubi_false	1	1			T30	1		-	-		-	-
ins	zero	pass	mubi_false	1822	1			T1	1		T4	3		T22	1
ins	zero	pass	mubi_true	365	1			T3	1		T26	1		T41	5

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded