Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T4
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T136,T119,T138
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T4
DataWait->AckPls	80	Covered	T1,T3,T4
DataWait->Disabled	107	Covered	T71,T151,T127
DataWait->Error	99	Covered	T8,T141,T54
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T3,T4
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T3,T4
DataWait	-	-	-	0	Covered	T3,T4,T9
AckPls	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T35,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1514718625	966254	0	0
FpvSecCmErrorStEscalate_A	1514718625	972617	0	0
u_state_regs_A	1514683546	1513592582	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514718625	966254	0	0
T1	5222	2086	0	0
T2	10570	0	0	0
T3	10773	0	0	0
T4	71869	0	0	0
T5	106701	0	0	0
T6	0	2708	0	0
T7	0	7972	0	0
T8	0	2849	0	0
T9	58366	0	0	0
T10	14126	0	0	0
T11	41608	0	0	0
T15	0	50568	0	0
T16	0	5964	0	0
T17	0	3234	0	0
T20	26488	0	0	0
T22	12502	0	0	0
T35	0	7741	0	0
T64	0	2260	0	0
T65	0	5956	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514718625	972617	0	0
T1	5222	2093	0	0
T2	10570	0	0	0
T3	10773	0	0	0
T4	71869	0	0	0
T5	106701	0	0	0
T6	0	2715	0	0
T7	0	7979	0	0
T8	0	2856	0	0
T9	58366	0	0	0
T10	14126	0	0	0
T11	41608	0	0	0
T15	0	51478	0	0
T16	0	5971	0	0
T17	0	3241	0	0
T20	26488	0	0	0
T22	12502	0	0	0
T35	0	7748	0	0
T64	0	2267	0	0
T65	0	5963	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1514683546	1513592582	0	0
T1	5110	3906	0	0
T2	10570	10101	0	0
T3	10773	10115	0	0
T4	71869	70287	0	0
T5	106701	100772	0	0
T9	58366	57694	0	0
T10	14126	13762	0	0
T11	41608	41251	0	0
T20	26488	25886	0	0
T22	12502	11991	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T43
DataWait	75	Covered	T3,T9,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T43
DataWait->AckPls	80	Covered	T3,T9,T43
DataWait->Disabled	107	Covered	T89,T90,T154
DataWait->Error	99	Covered	T94,T155,T126
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T9,T43
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T9,T43
Idle	-	1	0	-	Covered	T3,T9,T43
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T9,T43
DataWait	-	-	-	0	Covered	T3,T9,T43
AckPls	-	-	-	-	Covered	T3,T9,T43
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T44
DataWait	75	Covered	T3,T9,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T44
DataWait->AckPls	80	Covered	T3,T9,T44
DataWait->Disabled	107	Covered	T71,T151,T128
DataWait->Error	99	Covered	T8,T100,T82
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T9,T44
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T9,T44
Idle	-	1	0	-	Covered	T3,T9,T44
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T9,T44
DataWait	-	-	-	0	Covered	T3,T9,T44
AckPls	-	-	-	-	Covered	T3,T9,T44
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T26
DataWait	75	Covered	T3,T9,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T26
DataWait->AckPls	80	Covered	T3,T9,T26
DataWait->Disabled	107	Covered	T156,T157,T158
DataWait->Error	99	Covered	T16,T159,T160
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T9,T26
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T9,T26
Idle	-	1	0	-	Covered	T3,T9,T26
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T9,T26
DataWait	-	-	-	0	Covered	T3,T9,T26
AckPls	-	-	-	-	Covered	T3,T9,T26
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T20,T27
DataWait	75	Covered	T9,T20,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T20,T27
DataWait->AckPls	80	Covered	T9,T20,T27
DataWait->Disabled	107	Covered	T127,T161,T103
DataWait->Error	99	Covered	T93,T162
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T9,T20,T27
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T9,T20,T27
Idle	-	1	0	-	Covered	T9,T20,T27
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T9,T20,T27
DataWait	-	-	-	0	Covered	T9,T20,T27
AckPls	-	-	-	-	Covered	T9,T20,T27
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T4
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T138
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T4
DataWait->AckPls	80	Covered	T1,T3,T4
DataWait->Disabled	107	Covered	T129,T104,T163
DataWait->Error	99	Covered	T141,T54,T164
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T53
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T16,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T3,T4
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T3,T4
DataWait	-	-	-	0	Covered	T3,T4,T9
AckPls	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T35,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	136022	0	0
FpvSecCmErrorStEscalate_A	216388375	136931	0	0
u_state_regs_A	216353296	216197444	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	136022	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	344	0	0
T7	0	1096	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1063	0	0
T64	0	280	0	0
T65	0	808	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	136931	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	345	0	0
T7	0	1097	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1064	0	0
T64	0	281	0	0
T65	0	809	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216353296	216197444	0	0
T1	634	462	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T10,T44
DataWait	75	Covered	T3,T10,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T165
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T10,T44
DataWait->AckPls	80	Covered	T3,T10,T44
DataWait->Disabled	107	Covered	T166,T105,T167
DataWait->Error	99	Covered	T84,T168
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T10,T44
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T10,T44
Idle	-	1	0	-	Covered	T3,T10,T44
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T10,T44
DataWait	-	-	-	0	Covered	T3,T10,T44
AckPls	-	-	-	-	Covered	T3,T10,T44
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T26,T28

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T44
DataWait	75	Covered	T3,T9,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T1,T15,T35
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T136,T119
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T44
DataWait->AckPls	80	Covered	T3,T9,T44
DataWait->Disabled	107	Covered	T169,T170,T171
DataWait->Error	99	Covered	T56,T102,T172
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T15,T18,T19
EndPointClear->Disabled	107	Covered	T10,T152,T153
EndPointClear->Error	99	Covered	T15,T17,T98
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T9,T44
Idle->Disabled	107	Covered	T4,T10,T5
Idle->Error	99	Covered	T1,T35,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T9,T44
Idle	-	1	0	-	Covered	T3,T9,T44
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T9,T44
DataWait	-	-	-	0	Covered	T3,T9,T44
AckPls	-	-	-	-	Covered	T3,T9,T44
Error	-	-	-	-	Covered	T1,T15,T35
default	-	-	-	-	Covered	T15,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T35
0	1	Covered	T10,T26,T28
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216388375	138372	0	0
FpvSecCmErrorStEscalate_A	216388375	139281	0	0
u_state_regs_A	216388375	216232523	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	138372	0	0
T1	746	298	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	394	0	0
T7	0	1146	0	0
T8	0	407	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7224	0	0
T16	0	852	0	0
T17	0	462	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1113	0	0
T64	0	330	0	0
T65	0	858	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	139281	0	0
T1	746	299	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	395	0	0
T7	0	1147	0	0
T8	0	408	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7354	0	0
T16	0	853	0	0
T17	0	463	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T35	0	1114	0	0
T64	0	331	0	0
T65	0	859	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0