Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T75,T76
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T33,T39
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432136826	568870	0	0
DepthKnown_A	432776750	432465046	0	0
RvalidKnown_A	432776750	432465046	0	0
WreadyKnown_A	432776750	432465046	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	432491282	654762	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432136826	568870	0	0
T5	30486	0	0	0
T6	0	232	0	0
T9	16676	10966	0	0
T10	4036	1774	0	0
T11	11888	8553	0	0
T12	0	2579	0	0
T20	7568	3694	0	0
T21	0	1717	0	0
T22	3572	0	0	0
T26	3868	355	0	0
T27	1952	0	0	0
T43	0	10195	0	0
T50	1924	0	0	0
T51	58504	0	0	0
T77	0	3647	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432776750	432465046	0	0
T1	1492	1148	0	0
T2	3020	2886	0	0
T3	3078	2890	0	0
T4	20534	20082	0	0
T5	30486	28792	0	0
T9	16676	16484	0	0
T10	4036	3932	0	0
T11	11888	11786	0	0
T20	7568	7396	0	0
T22	3572	3426	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432776750	432465046	0	0
T1	1492	1148	0	0
T2	3020	2886	0	0
T3	3078	2890	0	0
T4	20534	20082	0	0
T5	30486	28792	0	0
T9	16676	16484	0	0
T10	4036	3932	0	0
T11	11888	11786	0	0
T20	7568	7396	0	0
T22	3572	3426	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432776750	432465046	0	0
T1	1492	1148	0	0
T2	3020	2886	0	0
T3	3078	2890	0	0
T4	20534	20082	0	0
T5	30486	28792	0	0
T9	16676	16484	0	0
T10	4036	3932	0	0
T11	11888	11786	0	0
T20	7568	7396	0	0
T22	3572	3426	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	432491282	654762	0	0
T5	30486	0	0	0
T9	16676	10966	0	0
T10	4036	1774	0	0
T11	11888	8553	0	0
T12	0	2579	0	0
T16	0	224	0	0
T20	7568	3694	0	0
T21	0	1717	0	0
T22	3572	0	0	0
T26	3868	355	0	0
T27	1952	0	0	0
T35	0	246	0	0
T43	0	10195	0	0
T50	1924	0	0	0
T51	58504	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T15,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T76,T78
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T79
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216068413	279715	0	0
DepthKnown_A	216388375	216232523	0	0
RvalidKnown_A	216388375	216232523	0	0
WreadyKnown_A	216388375	216232523	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216245641	322609	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216068413	279715	0	0
T5	15243	0	0	0
T6	0	62	0	0
T9	8338	5507	0	0
T10	2018	870	0	0
T11	5944	4266	0	0
T12	0	1259	0	0
T20	3784	1826	0	0
T21	0	849	0	0
T22	1786	0	0	0
T26	1934	179	0	0
T27	976	0	0	0
T43	0	5084	0	0
T50	962	0	0	0
T51	29252	0	0	0
T77	0	1789	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216245641	322609	0	0
T5	15243	0	0	0
T9	8338	5507	0	0
T10	2018	870	0	0
T11	5944	4266	0	0
T12	0	1259	0	0
T16	0	113	0	0
T20	3784	1826	0	0
T21	0	849	0	0
T22	1786	0	0	0
T26	1934	179	0	0
T27	976	0	0	0
T35	0	125	0	0
T43	0	5084	0	0
T50	962	0	0	0
T51	29252	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T75
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T39,T80
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216068413	289155	0	0
DepthKnown_A	216388375	216232523	0	0
RvalidKnown_A	216388375	216232523	0	0
WreadyKnown_A	216388375	216232523	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216245641	332153	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216068413	289155	0	0
T5	15243	0	0	0
T6	0	170	0	0
T9	8338	5459	0	0
T10	2018	904	0	0
T11	5944	4287	0	0
T12	0	1320	0	0
T20	3784	1868	0	0
T21	0	868	0	0
T22	1786	0	0	0
T26	1934	176	0	0
T27	976	0	0	0
T43	0	5111	0	0
T50	962	0	0	0
T51	29252	0	0	0
T77	0	1858	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216245641	332153	0	0
T5	15243	0	0	0
T9	8338	5459	0	0
T10	2018	904	0	0
T11	5944	4287	0	0
T12	0	1320	0	0
T16	0	111	0	0
T20	3784	1868	0	0
T21	0	868	0	0
T22	1786	0	0	0
T26	1934	176	0	0
T27	976	0	0	0
T35	0	121	0	0
T43	0	5111	0	0
T50	962	0	0	0
T51	29252	0	0	0