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Module Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_cmd_req_done


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_edn_fatal_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_regwen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_edn_enable


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_boot_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_auto_req_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_ctrl_cmd_fifo_rst


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_ins_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_boot_gen_cmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_reg_rdy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_rdy


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_sw_cmd_sts_cmd_sts


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_boot_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_auto_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_type


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_ack


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_hw_cmd_sts_cmd_sts


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_max_num_reqs_between_reseeds


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_edn_enable_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_boot_req_mode_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
tb.dut.u_reg.u_regwen.wr_en_data_arb
tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb
tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb
tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb
tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10CoveredT1,T3,T4 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T5
10CoveredT1,T3,T4 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T4,T5 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_cmd_req_done.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T4,T5 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_edn_fatal_err.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT23,T24,T25 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT23,T24,T25
10CoveredT23,T24,T25
11CoveredT1,T2,T3 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T24,T25
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_edn_enable.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_boot_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_auto_req_mode.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T4 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_cmd_fifo_rst.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT26,T27,T28 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T28 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T28
Branch Coverage for Instance : tb.dut.u_reg.u_boot_ins_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T26,T27,T28
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT26,T27,T28 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T28 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T27,T28
Branch Coverage for Instance : tb.dut.u_reg.u_boot_gen_cmd.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T26,T27,T28
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_reg_rdy.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_rdy.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_ack.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_sw_cmd_sts_cmd_sts.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_boot_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_auto_mode.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_type.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_ack.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_hw_cmd_sts_cmd_sts.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 1 1
51 unreachable
52 unreachable
53 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT9,T10,T11 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11
Branch Coverage for Instance : tb.dut.u_reg.u_max_num_reqs_between_reseeds.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_enable_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T30,T74
10CoveredT26,T29,T30 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT26,T30,T74
11CoveredT26,T30,T74 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T30,T74 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T29,T30
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_boot_req_mode_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT147,T148,T149
10CoveredT26,T29,T30 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT147,T148,T149
11CoveredT147,T148,T149 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT147,T148,T149 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T29,T30
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%