Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5707460

1

T1

34

T2

30

T3

277307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1689496	1			T1	177		T2	311		T3	76599
values[0x0]	2181497	1			T1	14		T2	11		T3	105963
values[0x1]	2534531	1			T1	15		T2	19		T3	122489

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	343171	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6062353

1

T1

84

T2

141

T3

292874

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25496	1			T3	1196		T101	603		T112	1
valid_sources[0x01]	26256	1			T3	1358		T9	1		T101	503
valid_sources[0x02]	25900	1			T1	1		T3	1086		T101	571
valid_sources[0x03]	23489	1			T3	1127		T23	2		T101	562
valid_sources[0x04]	25565	1			T3	1261		T9	3		T27	1
valid_sources[0x05]	24005	1			T1	1		T3	974		T9	1
valid_sources[0x06]	27015	1			T3	1111		T27	1		T101	521
valid_sources[0x07]	26054	1			T3	1109		T101	542		T112	5
valid_sources[0x08]	24338	1			T1	3		T3	1226		T16	1
valid_sources[0x09]	24246	1			T1	1		T3	1197		T27	2
valid_sources[0x0a]	25460	1			T1	2		T3	1431		T101	534
valid_sources[0x0b]	24656	1			T3	1206		T101	557		T112	1
valid_sources[0x0c]	25003	1			T1	3		T3	905		T101	556
valid_sources[0x0d]	26028	1			T1	2		T3	1024		T27	1
valid_sources[0x0e]	25715	1			T3	1031		T27	1		T101	553
valid_sources[0x0f]	24098	1			T1	1		T3	1154		T100	10
valid_sources[0x10]	25789	1			T1	1		T3	1143		T101	559
valid_sources[0x11]	22854	1			T3	1056		T101	600		T124	3
valid_sources[0x12]	24270	1			T1	1		T3	1183		T21	4
valid_sources[0x13]	22523	1			T3	1197		T101	551		T112	2
valid_sources[0x14]	26023	1			T1	1		T3	1004		T4	1
valid_sources[0x15]	24583	1			T3	1166		T22	380		T101	542
valid_sources[0x16]	26646	1			T3	1216		T16	1		T100	9
valid_sources[0x17]	23981	1			T3	1154		T101	556		T112	1
valid_sources[0x18]	26347	1			T3	1576		T101	554		T112	1
valid_sources[0x19]	24823	1			T1	1		T3	1159		T100	6
valid_sources[0x1a]	25390	1			T3	1209		T9	5		T27	3
valid_sources[0x1b]	25138	1			T1	1		T3	1397		T101	603
valid_sources[0x1c]	25761	1			T1	1		T3	1283		T9	1
valid_sources[0x1d]	23923	1			T1	1		T3	1099		T101	556
valid_sources[0x1e]	25003	1			T3	1224		T4	8		T27	1
valid_sources[0x1f]	27445	1			T3	1044		T101	575		T112	1
valid_sources[0x20]	24121	1			T1	1		T3	1339		T101	544
valid_sources[0x21]	23968	1			T3	1167		T16	2		T27	1
valid_sources[0x22]	25216	1			T3	1414		T16	1		T27	1
valid_sources[0x23]	26638	1			T3	1572		T27	1		T101	565
valid_sources[0x24]	24308	1			T3	1209		T27	1		T101	529
valid_sources[0x25]	23231	1			T1	1		T3	1117		T21	14
valid_sources[0x26]	25046	1			T1	2		T3	1031		T101	541
valid_sources[0x27]	28085	1			T3	1513		T101	562		T10	1
valid_sources[0x28]	24334	1			T1	2		T3	1315		T101	538
valid_sources[0x29]	25512	1			T1	3		T3	1163		T101	543
valid_sources[0x2a]	23404	1			T3	1019		T9	2		T101	595
valid_sources[0x2b]	26191	1			T3	1120		T101	622		T112	4
valid_sources[0x2c]	24206	1			T1	4		T3	1096		T101	571
valid_sources[0x2d]	25696	1			T3	862		T27	3		T101	543
valid_sources[0x2e]	24193	1			T1	3		T3	1220		T16	2
valid_sources[0x2f]	24492	1			T3	1169		T101	576		T112	2
valid_sources[0x30]	27131	1			T3	1583		T100	9		T101	506
valid_sources[0x31]	23211	1			T3	992		T101	579		T10	9
valid_sources[0x32]	24798	1			T3	1166		T101	567		T125	3
valid_sources[0x33]	25727	1			T1	1		T3	1041		T27	1
valid_sources[0x34]	25117	1			T3	1178		T100	3		T27	1
valid_sources[0x35]	25006	1			T3	832		T27	1		T101	541
valid_sources[0x36]	23683	1			T3	1219		T27	1		T101	532
valid_sources[0x37]	25999	1			T3	1380		T9	2		T23	3
valid_sources[0x38]	27064	1			T3	1169		T101	541		T10	1
valid_sources[0x39]	25814	1			T3	1098		T101	564		T112	1
valid_sources[0x3a]	25494	1			T3	1353		T101	610		T112	1
valid_sources[0x3b]	23526	1			T3	949		T101	574		T10	2
valid_sources[0x3c]	25250	1			T1	2		T3	1295		T101	535
valid_sources[0x3d]	26098	1			T1	1		T3	1078		T101	597
valid_sources[0x3e]	24756	1			T1	1		T3	917		T101	542
valid_sources[0x3f]	24714	1			T3	1290		T16	1		T27	1
valid_sources[0x40]	24449	1			T3	1220		T27	1		T101	539
valid_sources[0x41]	24403	1			T3	1246		T100	32		T101	585
valid_sources[0x42]	25175	1			T3	1172		T21	22		T101	568
valid_sources[0x43]	24349	1			T3	1125		T101	571		T124	2
valid_sources[0x44]	25912	1			T3	1084		T101	539		T28	2
valid_sources[0x45]	25785	1			T1	4		T3	1178		T16	3
valid_sources[0x46]	25096	1			T3	1003		T23	1		T27	2
valid_sources[0x47]	23006	1			T3	1096		T21	50		T27	1
valid_sources[0x48]	26329	1			T3	981		T101	562		T112	2
valid_sources[0x49]	24970	1			T1	1		T3	1319		T23	1
valid_sources[0x4a]	23965	1			T3	1148		T23	3		T27	1
valid_sources[0x4b]	24630	1			T1	1		T3	1178		T9	1
valid_sources[0x4c]	25543	1			T3	1115		T101	537		T112	1
valid_sources[0x4d]	23454	1			T3	1037		T100	4		T101	565
valid_sources[0x4e]	23794	1			T1	6		T3	1231		T101	583
valid_sources[0x4f]	24950	1			T1	1		T3	1395		T101	563
valid_sources[0x50]	24039	1			T1	4		T3	1161		T101	531
valid_sources[0x51]	25282	1			T3	1361		T101	534		T10	2
valid_sources[0x52]	24132	1			T1	1		T3	1233		T23	1
valid_sources[0x53]	24609	1			T1	1		T3	1474		T27	1
valid_sources[0x54]	23579	1			T1	3		T3	1169		T9	2
valid_sources[0x55]	23328	1			T1	2		T3	1202		T16	1
valid_sources[0x56]	25880	1			T3	966		T27	1		T101	532
valid_sources[0x57]	23790	1			T3	1161		T27	1		T101	554
valid_sources[0x58]	25525	1			T1	2		T3	1095		T101	574
valid_sources[0x59]	24726	1			T1	2		T3	1104		T101	558
valid_sources[0x5a]	25811	1			T3	1126		T23	1		T101	536
valid_sources[0x5b]	25052	1			T3	1300		T101	589		T126	4
valid_sources[0x5c]	27143	1			T3	1016		T101	591		T10	3
valid_sources[0x5d]	26568	1			T1	2		T3	952		T101	530
valid_sources[0x5e]	24080	1			T3	1195		T16	1		T23	7
valid_sources[0x5f]	24653	1			T1	1		T3	1313		T27	1
valid_sources[0x60]	25284	1			T3	1178		T101	539		T112	1
valid_sources[0x61]	25328	1			T3	1339		T101	579		T112	2
valid_sources[0x62]	25108	1			T3	762		T27	1		T101	558
valid_sources[0x63]	26433	1			T3	1357		T101	572		T112	1
valid_sources[0x64]	24672	1			T1	5		T3	1225		T101	543
valid_sources[0x65]	24509	1			T3	1026		T101	565		T112	2
valid_sources[0x66]	24556	1			T1	1		T3	1195		T101	552
valid_sources[0x67]	23347	1			T3	1206		T101	534		T147	1
valid_sources[0x68]	26364	1			T1	1		T2	341		T3	1308
valid_sources[0x69]	25423	1			T3	1424		T27	1		T101	584
valid_sources[0x6a]	22861	1			T1	2		T3	1058		T100	10
valid_sources[0x6b]	25830	1			T3	1325		T101	578		T10	4
valid_sources[0x6c]	27690	1			T3	1619		T101	539		T112	1
valid_sources[0x6d]	25142	1			T3	1087		T101	532		T112	2
valid_sources[0x6e]	25420	1			T1	6		T3	1172		T101	503
valid_sources[0x6f]	24935	1			T3	1439		T16	1		T101	540
valid_sources[0x70]	23753	1			T1	1		T3	1469		T27	2
valid_sources[0x71]	24105	1			T3	1127		T100	7		T101	570
valid_sources[0x72]	23624	1			T1	2		T3	1185		T101	537
valid_sources[0x73]	25267	1			T3	1261		T101	586		T10	3
valid_sources[0x74]	24316	1			T1	6		T3	1400		T101	584
valid_sources[0x75]	26313	1			T1	1		T3	1366		T27	1
valid_sources[0x76]	26652	1			T1	1		T3	1189		T101	562
valid_sources[0x77]	23260	1			T1	6		T3	1267		T101	559
valid_sources[0x78]	23399	1			T3	1174		T27	2		T101	526
valid_sources[0x79]	26813	1			T1	2		T3	1259		T16	1
valid_sources[0x7a]	24194	1			T1	3		T3	1046		T16	1
valid_sources[0x7b]	23481	1			T3	1406		T101	522		T125	2
valid_sources[0x7c]	26786	1			T3	1341		T27	2		T101	538
valid_sources[0x7d]	24194	1			T1	6		T3	996		T101	560
valid_sources[0x7e]	25747	1			T3	1374		T27	3		T101	531
valid_sources[0x7f]	22726	1			T3	989		T101	572		T10	3
valid_sources[0x80]	24262	1			T3	1188		T16	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1436267

1

T1

5

T2

4

T3

69467

values[0x0]

all_enables

biggest_size

2137480

1

T1

14

T2

10

T3

104324

values[0x1]

all_enables

biggest_size

2133713

1

T1

15

T2

16

T3

103516