Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2526	1			T3	23		T21	1		T100	1
non_zero_bins[1]	1753	1			T1	1		T3	23		T100	2
zero	8437	1			T2	1		T3	139		T9	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	449	1			T3	4		T100	1		T101	6
uni	3541	1			T3	61		T21	1		T22	1
gen	3888	1			T3	52		T9	3		T21	1
res	784	1			T3	7		T101	8		T10	2
ins	4054	1			T1	1		T2	1		T3	61

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8696

1

T1

1

T2

1

T3

140

mubi_true

4020

1

T3

45

T9

3

T21

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

26

1

T97

1

T35

1

T72

1

pass

12690

1

T1

1

T2

1

T3

185

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	103	1			T3	1		T101	2		T144	1
upd	non_zero_bins[0]	pass	mubi_true	104	1			T101	2		T144	2		T111	2
upd	non_zero_bins[1]	pass	mubi_false	68	1			T3	1		T100	1		T101	1
upd	non_zero_bins[1]	pass	mubi_true	89	1			T111	1		T187	5		T188	1
upd	zero	pass	mubi_false	44	1			T3	1		T114	1		T190	1
upd	zero	pass	mubi_true	41	1			T3	1		T101	1		T144	1
uni	zero	fail	mubi_false	8	1			T97	1		T150	1		T248	1
uni	zero	pass	mubi_false	2541	1			T3	45		T21	1		T22	1
uni	zero	pass	mubi_true	992	1			T3	16		T100	2		T101	9
gen	non_zero_bins[0]	pass	mubi_false	498	1			T3	2		T101	6		T125	2
gen	non_zero_bins[0]	pass	mubi_true	464	1			T3	4		T100	1		T101	1
gen	non_zero_bins[1]	pass	mubi_false	323	1			T3	4		T101	5		T11	1
gen	non_zero_bins[1]	pass	mubi_true	303	1			T3	4		T101	3		T10	1
gen	zero	fail	mubi_false	10	1			T35	1		T72	1		T249	1
gen	zero	pass	mubi_false	1897	1			T3	37		T9	1		T16	1
gen	zero	pass	mubi_true	393	1			T3	1		T9	2		T21	1
res	non_zero_bins[0]	pass	mubi_false	170	1			T101	2		T18	2		T20	2
res	non_zero_bins[0]	pass	mubi_true	190	1			T3	4		T101	3		T10	2
res	non_zero_bins[1]	pass	mubi_false	134	1			T143	1		T41	1		T187	1
res	non_zero_bins[1]	pass	mubi_true	138	1			T101	1		T11	2		T19	2
res	zero	fail	mubi_false	4	1			T184	1		T250	1		T251	1
res	zero	pass	mubi_false	82	1			T3	3		T131	1		T111	1
res	zero	pass	mubi_true	66	1			T101	2		T28	3		T125	1
ins	non_zero_bins[0]	pass	mubi_false	516	1			T3	4		T21	1		T101	7
ins	non_zero_bins[0]	pass	mubi_true	481	1			T3	8		T10	1		T28	1
ins	non_zero_bins[1]	pass	mubi_false	351	1			T1	1		T3	7		T100	1
ins	non_zero_bins[1]	pass	mubi_true	347	1			T3	7		T27	1		T101	6
ins	zero	fail	mubi_false	4	1			T80	1		T252	1		T253	1
ins	zero	pass	mubi_false	1943	1			T2	1		T3	35		T9	1
ins	zero	pass	mubi_true	412	1			T9	1		T21	1		T22	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded