Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	708380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5858985

1

T1

27

T2

2

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1726689	1			T1	126		T2	1		T3	77
values[0x0]	2239008	1			T1	17		T2	2		T3	2
values[0x1]	2601668	1			T1	11		T2	3		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	345986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6221379

1

T1

69

T2

4

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26336	1			T3	1		T11	2		T99	2
valid_sources[0x01]	25733	1			T11	1		T99	1		T21	1
valid_sources[0x02]	25722	1			T3	6		T8	1		T10	2
valid_sources[0x03]	23898	1			T11	1		T99	2		T100	1
valid_sources[0x04]	26921	1			T10	1		T11	3		T99	1
valid_sources[0x05]	24063	1			T8	1		T4	2		T99	5
valid_sources[0x06]	24019	1			T11	1		T99	1		T20	1
valid_sources[0x07]	26475	1			T10	5		T99	1		T138	1
valid_sources[0x08]	24244	1			T8	1		T11	1		T5	1
valid_sources[0x09]	26299	1			T8	1		T10	2		T99	4
valid_sources[0x0a]	25198	1			T3	1		T99	2		T146	2
valid_sources[0x0b]	26055	1			T99	6		T115	659		T147	2
valid_sources[0x0c]	24786	1			T4	1		T105	1		T138	2
valid_sources[0x0d]	25099	1			T8	2		T24	1		T99	3
valid_sources[0x0e]	24959	1			T8	1		T4	2		T18	3
valid_sources[0x0f]	25814	1			T8	1		T4	2		T11	1
valid_sources[0x10]	26659	1			T3	3		T99	6		T102	3
valid_sources[0x11]	24646	1			T8	1		T11	1		T99	1
valid_sources[0x12]	27788	1			T99	1		T146	1		T115	610
valid_sources[0x13]	25597	1			T3	4		T11	2		T99	1
valid_sources[0x14]	27049	1			T11	1		T99	4		T115	681
valid_sources[0x15]	25923	1			T3	3		T11	1		T99	2
valid_sources[0x16]	26208	1			T11	1		T99	1		T138	7
valid_sources[0x17]	25563	1			T3	2		T11	1		T18	1
valid_sources[0x18]	25875	1			T3	1		T4	3		T115	663
valid_sources[0x19]	26132	1			T8	3		T11	2		T99	3
valid_sources[0x1a]	26583	1			T10	3		T11	1		T99	2
valid_sources[0x1b]	25884	1			T11	1		T99	4		T20	3
valid_sources[0x1c]	25721	1			T4	2		T11	1		T99	3
valid_sources[0x1d]	27014	1			T8	1		T105	1		T20	1
valid_sources[0x1e]	23479	1			T1	6		T99	1		T105	1
valid_sources[0x1f]	27021	1			T10	5		T11	1		T99	2
valid_sources[0x20]	25367	1			T99	3		T21	2		T146	1
valid_sources[0x21]	25518	1			T8	4		T11	1		T99	1
valid_sources[0x22]	25912	1			T11	1		T99	2		T105	1
valid_sources[0x23]	25515	1			T8	2		T10	1		T11	1
valid_sources[0x24]	25406	1			T8	1		T4	3		T10	3
valid_sources[0x25]	25010	1			T10	1		T99	1		T138	3
valid_sources[0x26]	25350	1			T9	182		T10	2		T11	2
valid_sources[0x27]	25037	1			T1	7		T99	5		T105	1
valid_sources[0x28]	26139	1			T10	1		T99	5		T109	1
valid_sources[0x29]	26661	1			T11	2		T99	2		T20	2
valid_sources[0x2a]	25327	1			T8	1		T10	6		T11	1
valid_sources[0x2b]	24921	1			T4	2		T104	360		T99	3
valid_sources[0x2c]	26326	1			T99	5		T115	687		T147	4
valid_sources[0x2d]	26007	1			T5	1		T99	4		T115	693
valid_sources[0x2e]	24917	1			T11	2		T99	2		T94	2
valid_sources[0x2f]	26476	1			T4	1		T99	2		T138	2
valid_sources[0x30]	24711	1			T10	1		T11	1		T5	2
valid_sources[0x31]	24650	1			T8	1		T99	2		T105	1
valid_sources[0x32]	24403	1			T10	2		T99	5		T109	1
valid_sources[0x33]	25017	1			T10	2		T24	1		T99	1
valid_sources[0x34]	26280	1			T8	1		T4	1		T11	1
valid_sources[0x35]	25650	1			T3	2		T11	1		T20	1
valid_sources[0x36]	26935	1			T11	1		T115	690		T147	2
valid_sources[0x37]	26752	1			T4	5		T11	1		T99	3
valid_sources[0x38]	24640	1			T99	2		T123	3		T94	1
valid_sources[0x39]	24735	1			T2	2		T10	1		T11	2
valid_sources[0x3a]	23556	1			T11	1		T99	3		T21	1
valid_sources[0x3b]	24844	1			T10	4		T11	1		T5	1
valid_sources[0x3c]	26766	1			T99	3		T20	2		T94	12
valid_sources[0x3d]	24470	1			T10	6		T99	3		T109	1
valid_sources[0x3e]	25236	1			T8	2		T11	2		T99	3
valid_sources[0x3f]	26648	1			T8	1		T11	1		T20	1
valid_sources[0x40]	26794	1			T11	5		T99	3		T105	1
valid_sources[0x41]	27108	1			T5	1		T99	2		T115	666
valid_sources[0x42]	25947	1			T4	1		T99	1		T115	726
valid_sources[0x43]	26850	1			T10	3		T18	1		T99	2
valid_sources[0x44]	25149	1			T11	1		T99	5		T115	635
valid_sources[0x45]	26080	1			T11	4		T99	2		T115	694
valid_sources[0x46]	26783	1			T4	2		T11	1		T99	2
valid_sources[0x47]	26269	1			T99	3		T123	1		T115	618
valid_sources[0x48]	24802	1			T8	1		T99	3		T20	1
valid_sources[0x49]	25124	1			T1	12		T4	2		T11	1
valid_sources[0x4a]	25349	1			T3	1		T10	1		T99	1
valid_sources[0x4b]	25768	1			T11	1		T99	5		T115	744
valid_sources[0x4c]	25199	1			T11	3		T99	1		T19	1
valid_sources[0x4d]	25638	1			T1	7		T3	2		T99	7
valid_sources[0x4e]	26733	1			T99	2		T105	1		T138	2
valid_sources[0x4f]	25500	1			T8	2		T4	1		T11	2
valid_sources[0x50]	26813	1			T4	2		T99	3		T19	1
valid_sources[0x51]	25262	1			T10	1		T11	1		T146	2
valid_sources[0x52]	27151	1			T11	1		T99	4		T105	2
valid_sources[0x53]	25323	1			T8	1		T11	2		T99	2
valid_sources[0x54]	25755	1			T3	2		T99	1		T115	669
valid_sources[0x55]	25627	1			T8	1		T99	1		T20	2
valid_sources[0x56]	25481	1			T3	1		T99	4		T20	1
valid_sources[0x57]	25047	1			T11	1		T99	2		T25	4
valid_sources[0x58]	24468	1			T10	1		T11	2		T99	2
valid_sources[0x59]	25328	1			T99	4		T105	1		T118	9
valid_sources[0x5a]	24682	1			T4	1		T21	1		T109	1
valid_sources[0x5b]	25859	1			T8	2		T99	3		T115	634
valid_sources[0x5c]	26436	1			T99	6		T20	3		T138	3
valid_sources[0x5d]	26277	1			T3	3		T99	2		T20	1
valid_sources[0x5e]	24220	1			T99	1		T123	2		T115	716
valid_sources[0x5f]	25150	1			T11	2		T99	4		T22	77
valid_sources[0x60]	26132	1			T8	1		T11	2		T5	2
valid_sources[0x61]	25772	1			T11	2		T99	6		T105	1
valid_sources[0x62]	25381	1			T11	1		T18	1		T99	2
valid_sources[0x63]	26775	1			T2	3		T4	1		T11	1
valid_sources[0x64]	25708	1			T24	1		T99	4		T102	4
valid_sources[0x65]	24456	1			T8	1		T99	6		T109	1
valid_sources[0x66]	24649	1			T11	2		T99	5		T20	1
valid_sources[0x67]	25727	1			T3	1		T8	2		T11	1
valid_sources[0x68]	26661	1			T11	1		T99	2		T118	7
valid_sources[0x69]	25173	1			T8	1		T99	1		T105	1
valid_sources[0x6a]	24493	1			T11	2		T5	1		T99	3
valid_sources[0x6b]	26143	1			T8	2		T11	2		T99	1
valid_sources[0x6c]	27604	1			T10	4		T11	1		T99	11
valid_sources[0x6d]	26774	1			T99	3		T94	1		T115	697
valid_sources[0x6e]	25006	1			T4	3		T11	2		T99	2
valid_sources[0x6f]	24546	1			T8	2		T11	7		T99	3
valid_sources[0x70]	26808	1			T99	3		T20	1		T115	669
valid_sources[0x71]	24220	1			T10	1		T11	1		T99	2
valid_sources[0x72]	25089	1			T3	2		T8	1		T11	2
valid_sources[0x73]	26130	1			T8	6		T10	3		T11	2
valid_sources[0x74]	25205	1			T8	2		T4	2		T5	4
valid_sources[0x75]	25413	1			T1	20		T10	2		T5	2
valid_sources[0x76]	26720	1			T99	2		T115	655		T129	1
valid_sources[0x77]	26070	1			T8	1		T11	1		T99	2
valid_sources[0x78]	23978	1			T99	2		T115	678		T129	1
valid_sources[0x79]	26611	1			T8	2		T11	2		T99	5
valid_sources[0x7a]	25074	1			T94	12		T19	2		T115	676
valid_sources[0x7b]	24620	1			T3	1		T10	1		T11	2
valid_sources[0x7c]	25196	1			T10	3		T24	2		T99	4
valid_sources[0x7d]	27119	1			T11	1		T5	1		T99	2
valid_sources[0x7e]	24630	1			T3	1		T11	2		T99	1
valid_sources[0x7f]	25474	1			T8	4		T11	1		T99	3
valid_sources[0x80]	26541	1			T11	2		T99	2		T25	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1474539

1

T1

4

T3

4

T8

3

values[0x0]

all_enables

biggest_size

2194341

1

T1

13

T3

1

T8

39

values[0x1]

all_enables

biggest_size

2190105

1

T1

10

T2

2

T3

2