Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2704	1			T1	3		T8	5		T9	2
non_zero_bins[1]	1921	1			T8	1		T9	2		T10	10
zero	8688	1			T1	2		T2	3		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	512	1			T99	1		T115	3		T121	1
uni	3715	1			T1	2		T3	1		T9	1
gen	4065	1			T1	1		T2	1		T3	1
res	852	1			T8	4		T9	2		T10	2
ins	4169	1			T1	2		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9116

1

T1

4

T2

2

T3

3

mubi_true

4197

1

T1

1

T2

1

T8

6

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13313

1

T1

5

T2

3

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	119	1			T99	1		T121	1		T124	1
upd	non_zero_bins[0]	pass	mubi_true	113	1			T115	2		T124	1		T116	4
upd	non_zero_bins[1]	pass	mubi_false	76	1			T115	1		T129	1		T150	1
upd	non_zero_bins[1]	pass	mubi_true	102	1			T150	2		T116	2		T117	2
upd	zero	pass	mubi_false	50	1			T116	1		T188	1		T241	1
upd	zero	pass	mubi_true	52	1			T242	1		T116	1		T152	2
uni	zero	pass	mubi_false	2755	1			T1	2		T3	1		T9	1
uni	zero	pass	mubi_true	960	1			T99	2		T20	1		T123	1
gen	non_zero_bins[0]	pass	mubi_false	532	1			T99	3		T122	1		T94	1
gen	non_zero_bins[0]	pass	mubi_true	471	1			T1	1		T9	1		T10	1
gen	non_zero_bins[1]	pass	mubi_false	369	1			T11	6		T99	1		T118	1
gen	non_zero_bins[1]	pass	mubi_true	344	1			T10	7		T99	1		T138	3
gen	zero	pass	mubi_false	1903	1			T3	1		T9	19		T5	1
gen	zero	pass	mubi_true	446	1			T2	1		T104	1		T99	1
res	non_zero_bins[0]	pass	mubi_false	219	1			T99	1		T22	3		T122	2
res	non_zero_bins[0]	pass	mubi_true	192	1			T8	4		T99	1		T94	1
res	non_zero_bins[1]	pass	mubi_false	135	1			T11	2		T104	1		T99	1
res	non_zero_bins[1]	pass	mubi_true	138	1			T9	2		T10	2		T99	1
res	zero	pass	mubi_false	96	1			T146	1		T115	1		T23	1
res	zero	pass	mubi_true	72	1			T141	1		T150	1		T53	4
ins	non_zero_bins[0]	pass	mubi_false	539	1			T1	2		T9	1		T11	1
ins	non_zero_bins[0]	pass	mubi_true	519	1			T8	1		T99	1		T123	2
ins	non_zero_bins[1]	pass	mubi_false	399	1			T99	1		T20	1		T118	1
ins	non_zero_bins[1]	pass	mubi_true	358	1			T8	1		T10	1		T20	1
ins	zero	pass	mubi_false	1924	1			T2	2		T3	1		T5	1
ins	zero	pass	mubi_true	430	1			T99	3		T22	1		T21	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded