Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T3,T8,T9
DataWait 75 Covered T3,T8,T9
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T90
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T3,T8,T9
DataWait->AckPls 80 Covered T3,T8,T9
DataWait->Disabled 107 Covered T29,T47,T48
DataWait->Error 99 Covered T98,T37,T62
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T3,T8,T9
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T3,T8,T9
Idle - 1 0 - Covered T3,T8,T9
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T3,T8,T9
DataWait - - - 0 Covered T3,T8,T9
AckPls - - - - Covered T3,T8,T9
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T43,T65


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 1621291196 1081286 0 0
FpvSecCmErrorStEscalate_A 1621291196 1089490 0 0
u_state_regs_A 1621253208 1619999459 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1621291196 1081286 0 0
T4 9555 3773 0 0
T5 13902 7476 0 0
T6 0 4641 0 0
T7 0 1750 0 0
T9 15757 0 0 0
T10 25788 0 0 0
T11 14448 0 0 0
T13 0 8043 0 0
T14 0 8043 0 0
T18 9457 0 0 0
T24 8078 3626 0 0
T98 0 1764 0 0
T99 143717 0 0 0
T102 0 7490 0 0
T103 0 4186 0 0
T104 18340 0 0 0
T105 11634 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1621291196 1089490 0 0
T4 9555 3780 0 0
T5 13902 7483 0 0
T6 0 4648 0 0
T7 0 1757 0 0
T9 15757 0 0 0
T10 25788 0 0 0
T11 14448 0 0 0
T13 0 8050 0 0
T14 0 8050 0 0
T18 9457 0 0 0
T24 8078 3633 0 0
T98 0 1771 0 0
T99 143717 0 0 0
T102 0 7497 0 0
T103 0 4193 0 0
T104 18340 0 0 0
T105 11634 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1621253208 1619999459 0 0
T1 12789 11697 0 0
T2 7091 6496 0 0
T3 9765 9240 0 0
T4 9377 8481 0 0
T5 13790 12796 0 0
T8 16541 15988 0 0
T9 15757 15162 0 0
T10 25788 25109 0 0
T11 14448 13853 0 0
T18 9457 8834 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T3,T9,T10
DataWait 75 Covered T3,T9,T10
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T3,T9,T10
DataWait->AckPls 80 Covered T3,T9,T10
DataWait->Disabled 107 Covered T162,T163,T164
DataWait->Error 99 Covered T37,T165,T166
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T3,T9,T10
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T3,T9,T10
Idle - 1 0 - Covered T3,T9,T10
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T3,T9,T10
DataWait - - - 0 Covered T3,T9,T10
AckPls - - - - Covered T3,T9,T10
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T43,T65


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 152498 0 0
FpvSecCmErrorStEscalate_A 231613028 153670 0 0
u_state_regs_A 231575040 231395933 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 152498 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 153670 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231575040 231395933 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1187 1059 0 0
T5 1874 1732 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T8,T9,T10
DataWait 75 Covered T8,T9,T10
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T8,T9,T10
DataWait->AckPls 80 Covered T8,T9,T10
DataWait->Disabled 107 Covered T66,T167,T49
DataWait->Error 99 Covered T98,T62,T38
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T8,T9,T10
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T8,T9,T10
Idle - 1 0 - Covered T8,T9,T10
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T8,T9,T10
DataWait - - - 0 Covered T8,T9,T10
AckPls - - - - Covered T8,T9,T10
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T2,T9,T10
DataWait 75 Covered T2,T9,T10
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T9,T10
DataWait->AckPls 80 Covered T2,T9,T10
DataWait->Disabled 107 Covered T91,T168,T169
DataWait->Error 99 Covered T7,T170,T171
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T9,T10
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T9,T10
Idle - 1 0 - Covered T2,T9,T10
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T9,T10
DataWait - - - 0 Covered T2,T9,T10
AckPls - - - - Covered T2,T9,T10
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T9,T10,T104
DataWait 75 Covered T9,T10,T104
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T10,T104
DataWait->AckPls 80 Covered T9,T10,T104
DataWait->Disabled 107 Covered T29,T78,T172
DataWait->Error 99 Covered T88,T64,T173
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T10,T104
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T10,T104
Idle - 1 0 - Covered T9,T10,T104
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T10,T104
DataWait - - - 0 Covered T9,T10,T104
AckPls - - - - Covered T9,T10,T104
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T9,T10,T104
DataWait 75 Covered T9,T10,T104
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T10,T104
DataWait->AckPls 80 Covered T9,T10,T104
DataWait->Disabled 107 Covered T32,T174
DataWait->Error 99 Covered T86,T175
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T10,T104
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T10,T104
Idle - 1 0 - Covered T9,T10,T104
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T10,T104
DataWait - - - 0 Covered T9,T10,T104
AckPls - - - - Covered T9,T10,T104
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T9,T10,T5
DataWait 75 Covered T9,T10,T5
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T10,T5
DataWait->AckPls 80 Covered T9,T10,T5
DataWait->Disabled 107 Covered T22,T176
DataWait->Error 99 Covered T177
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T10,T5
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T10,T5
Idle - 1 0 - Covered T9,T10,T5
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T10,T5
DataWait - - - 0 Covered T9,T10,T104
AckPls - - - - Covered T9,T10,T5
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T8,T4

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T9,T10,T104
DataWait 75 Covered T9,T10,T104
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T24
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T90
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T9,T10,T104
DataWait->AckPls 80 Covered T9,T10,T104
DataWait->Disabled 107 Covered T47,T48,T178
DataWait->Error 99 Covered T85,T179,T180
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T15,T16,T17
EndPointClear->Disabled 107 Covered T147,T149,T161
EndPointClear->Error 99 Covered T4,T14,T15
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T9,T10,T104
Idle->Disabled 107 Covered T1,T2,T8
Idle->Error 99 Covered T5,T24,T102



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T9,T10,T104
Idle - 1 0 - Covered T9,T10,T104
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T9,T10,T104
DataWait - - - 0 Covered T9,T10,T104
AckPls - - - - Covered T9,T10,T104
Error - - - - Covered T4,T5,T24
default - - - - Covered T15,T16,T17


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T24
0 1 Covered T2,T8,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 231613028 154798 0 0
FpvSecCmErrorStEscalate_A 231613028 155970 0 0
u_state_regs_A 231613028 231433921 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 154798 0 0
T4 1365 539 0 0
T5 1986 1068 0 0
T6 0 663 0 0
T7 0 250 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1149 0 0
T14 0 1149 0 0
T18 1351 0 0 0
T24 1154 518 0 0
T98 0 252 0 0
T99 20531 0 0 0
T102 0 1070 0 0
T103 0 598 0 0
T104 2620 0 0 0
T105 1662 0 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 155970 0 0
T4 1365 540 0 0
T5 1986 1069 0 0
T6 0 664 0 0
T7 0 251 0 0
T9 2251 0 0 0
T10 3684 0 0 0
T11 2064 0 0 0
T13 0 1150 0 0
T14 0 1150 0 0
T18 1351 0 0 0
T24 1154 519 0 0
T98 0 253 0 0
T99 20531 0 0 0
T102 0 1071 0 0
T103 0 599 0 0
T104 2620 0 0 0
T105 1662 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231613028 231433921 0 0
T1 1827 1671 0 0
T2 1013 928 0 0
T3 1395 1320 0 0
T4 1365 1237 0 0
T5 1986 1844 0 0
T8 2363 2284 0 0
T9 2251 2166 0 0
T10 3684 3587 0 0
T11 2064 1979 0 0
T18 1351 1262 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%