Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T109,T112,T113
1	1	0	Not Covered
1	1	1	Covered	T8,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T100,T110,T114
1	0	1	Covered	T8,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462502010	1481613	0	0
DepthKnown_A	463226056	462867842	0	0
RvalidKnown_A	463226056	462867842	0	0
WreadyKnown_A	463226056	462867842	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	462869064	1565405	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462502010	1481613	0	0
T4	512	194	0	0
T5	670	0	0	0
T8	4726	2751	0	0
T9	4502	1978	0	0
T10	7368	3203	0	0
T11	4128	1021	0	0
T18	2702	0	0	0
T19	0	691	0	0
T22	0	2600	0	0
T24	704	0	0	0
T99	41062	0	0	0
T104	5240	0	0	0
T120	0	8405	0	0
T122	0	9795	0	0
T138	0	1562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463226056	462867842	0	0
T1	3654	3342	0	0
T2	2026	1856	0	0
T3	2790	2640	0	0
T4	2730	2474	0	0
T5	3972	3688	0	0
T8	4726	4568	0	0
T9	4502	4332	0	0
T10	7368	7174	0	0
T11	4128	3958	0	0
T18	2702	2524	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463226056	462867842	0	0
T1	3654	3342	0	0
T2	2026	1856	0	0
T3	2790	2640	0	0
T4	2730	2474	0	0
T5	3972	3688	0	0
T8	4726	4568	0	0
T9	4502	4332	0	0
T10	7368	7174	0	0
T11	4128	3958	0	0
T18	2702	2524	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463226056	462867842	0	0
T1	3654	3342	0	0
T2	2026	1856	0	0
T3	2790	2640	0	0
T4	2730	2474	0	0
T5	3972	3688	0	0
T8	4726	4568	0	0
T9	4502	4332	0	0
T10	7368	7174	0	0
T11	4128	3958	0	0
T18	2702	2524	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	462869064	1565405	0	0
T4	2730	1091	0	0
T5	3972	0	0	0
T8	4726	2751	0	0
T9	4502	1978	0	0
T10	7368	3203	0	0
T11	4128	1021	0	0
T18	2702	0	0	0
T19	0	342	0	0
T22	0	2600	0	0
T24	2308	0	0	0
T99	41062	0	0	0
T102	0	220	0	0
T104	5240	0	0	0
T109	0	22	0	0
T122	0	9795	0	0
T138	0	1562	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T109,T112,T113
1	1	0	Not Covered
1	1	1	Covered	T8,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T100,T142,T143
1	0	1	Covered	T8,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	231251005	735686	0	0
DepthKnown_A	231613028	231433921	0	0
RvalidKnown_A	231613028	231433921	0	0
WreadyKnown_A	231613028	231433921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	231434532	777396	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231251005	735686	0	0
T4	256	43	0	0
T5	335	0	0	0
T8	2363	1312	0	0
T9	2251	1003	0	0
T10	3684	1581	0	0
T11	2064	506	0	0
T18	1351	0	0	0
T19	0	349	0	0
T22	0	1238	0	0
T24	352	0	0	0
T99	20531	0	0	0
T104	2620	0	0	0
T120	0	4200	0	0
T122	0	4878	0	0
T138	0	787	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	231434532	777396	0	0
T4	1365	491	0	0
T5	1986	0	0	0
T8	2363	1312	0	0
T9	2251	1003	0	0
T10	3684	1581	0	0
T11	2064	506	0	0
T18	1351	0	0	0
T22	0	1238	0	0
T24	1154	0	0	0
T99	20531	0	0	0
T102	0	111	0	0
T104	2620	0	0	0
T109	0	22	0	0
T122	0	4878	0	0
T138	0	787	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T8,T4,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T144
1	1	0	Not Covered
1	1	1	Covered	T8,T4,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T114
1	0	1	Covered	T8,T4,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T8,T4,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	231251005	745927	0	0
DepthKnown_A	231613028	231433921	0	0
RvalidKnown_A	231613028	231433921	0	0
WreadyKnown_A	231613028	231433921	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	231434532	788009	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231251005	745927	0	0
T4	256	151	0	0
T5	335	0	0	0
T8	2363	1439	0	0
T9	2251	975	0	0
T10	3684	1622	0	0
T11	2064	515	0	0
T18	1351	0	0	0
T19	0	342	0	0
T22	0	1362	0	0
T24	352	0	0	0
T99	20531	0	0	0
T104	2620	0	0	0
T120	0	4205	0	0
T122	0	4917	0	0
T138	0	775	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	231434532	788009	0	0
T4	1365	600	0	0
T5	1986	0	0	0
T8	2363	1439	0	0
T9	2251	975	0	0
T10	3684	1622	0	0
T11	2064	515	0	0
T18	1351	0	0	0
T19	0	342	0	0
T22	0	1362	0	0
T24	1154	0	0	0
T99	20531	0	0	0
T102	0	109	0	0
T104	2620	0	0	0
T122	0	4917	0	0
T138	0	775	0	0