Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	704528	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5670715

1

T1

33

T2

36

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1690360	1			T1	44		T2	94		T3	5
values[0x0]	2166430	1			T1	18		T2	17		T3	6
values[0x1]	2518453	1			T1	15		T2	16		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	349466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6025777

1

T1

43

T2

66

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24710	1			T19	2		T21	1		T9	1
valid_sources[0x01]	25281	1			T11	1		T133	7		T99	64
valid_sources[0x02]	26105	1			T144	2		T99	49		T118	1
valid_sources[0x03]	24607	1			T11	2		T23	1		T144	1
valid_sources[0x04]	22939	1			T3	1		T19	1		T10	12
valid_sources[0x05]	25438	1			T21	3		T23	1		T9	1
valid_sources[0x06]	25428	1			T1	2		T11	1		T99	74
valid_sources[0x07]	25809	1			T19	2		T117	1		T5	14
valid_sources[0x08]	27109	1			T1	1		T117	2		T133	11
valid_sources[0x09]	23507	1			T99	61		T206	2		T123	1
valid_sources[0x0a]	24019	1			T144	12		T133	2		T99	42
valid_sources[0x0b]	24308	1			T1	2		T133	2		T98	2
valid_sources[0x0c]	25477	1			T21	1		T5	15		T99	48
valid_sources[0x0d]	25286	1			T3	2		T133	2		T99	52
valid_sources[0x0e]	24101	1			T21	1		T143	2		T99	57
valid_sources[0x0f]	25902	1			T1	1		T99	41		T113	406
valid_sources[0x10]	25304	1			T1	1		T23	1		T9	1
valid_sources[0x11]	24975	1			T21	1		T4	1		T5	1
valid_sources[0x12]	25487	1			T19	1		T21	2		T22	1
valid_sources[0x13]	25171	1			T1	1		T19	2		T99	31
valid_sources[0x14]	25765	1			T1	3		T19	2		T99	55
valid_sources[0x15]	23079	1			T144	8		T5	1		T99	65
valid_sources[0x16]	23809	1			T1	1		T143	2		T99	58
valid_sources[0x17]	24735	1			T1	1		T133	3		T99	54
valid_sources[0x18]	25009	1			T1	1		T11	6		T99	67
valid_sources[0x19]	25475	1			T23	1		T9	1		T99	63
valid_sources[0x1a]	25125	1			T23	1		T99	58		T206	1
valid_sources[0x1b]	24104	1			T19	1		T23	2		T4	1
valid_sources[0x1c]	22446	1			T1	1		T19	1		T99	54
valid_sources[0x1d]	25549	1			T19	1		T99	57		T118	1
valid_sources[0x1e]	25015	1			T11	1		T4	1		T117	4
valid_sources[0x1f]	25837	1			T1	1		T4	1		T117	2
valid_sources[0x20]	24854	1			T23	1		T117	1		T99	45
valid_sources[0x21]	26195	1			T11	5		T23	1		T143	2
valid_sources[0x22]	23045	1			T1	1		T21	1		T9	2
valid_sources[0x23]	26818	1			T23	3		T144	13		T117	1
valid_sources[0x24]	25654	1			T1	1		T19	1		T11	4
valid_sources[0x25]	23143	1			T117	1		T99	70		T118	3
valid_sources[0x26]	24078	1			T19	1		T8	49		T21	2
valid_sources[0x27]	26026	1			T1	1		T21	1		T9	1
valid_sources[0x28]	26550	1			T19	1		T21	1		T133	4
valid_sources[0x29]	25720	1			T1	1		T117	2		T99	61
valid_sources[0x2a]	25160	1			T4	1		T9	2		T144	1
valid_sources[0x2b]	27493	1			T23	2		T117	1		T99	61
valid_sources[0x2c]	24270	1			T99	46		T118	4		T28	1
valid_sources[0x2d]	23604	1			T4	1		T9	2		T99	61
valid_sources[0x2e]	24094	1			T21	1		T23	1		T117	1
valid_sources[0x2f]	26038	1			T1	1		T21	3		T144	15
valid_sources[0x30]	22897	1			T9	1		T99	57		T118	1
valid_sources[0x31]	26757	1			T23	1		T117	2		T99	58
valid_sources[0x32]	25852	1			T19	1		T23	1		T9	1
valid_sources[0x33]	26776	1			T129	5		T98	1		T99	64
valid_sources[0x34]	24688	1			T99	43		T118	3		T70	1
valid_sources[0x35]	25143	1			T9	1		T99	37		T123	1
valid_sources[0x36]	25025	1			T4	1		T117	6		T99	40
valid_sources[0x37]	23483	1			T19	2		T11	3		T99	56
valid_sources[0x38]	23960	1			T1	1		T9	1		T128	14
valid_sources[0x39]	24886	1			T19	1		T117	1		T99	58
valid_sources[0x3a]	24168	1			T99	74		T123	1		T119	1
valid_sources[0x3b]	23285	1			T21	3		T9	1		T5	8
valid_sources[0x3c]	25848	1			T21	1		T133	4		T99	77
valid_sources[0x3d]	26666	1			T19	1		T117	1		T133	13
valid_sources[0x3e]	25337	1			T23	1		T117	1		T99	54
valid_sources[0x3f]	24291	1			T143	1		T99	45		T119	4
valid_sources[0x40]	24256	1			T9	1		T98	2		T99	62
valid_sources[0x41]	26929	1			T21	1		T9	2		T144	8
valid_sources[0x42]	25461	1			T23	1		T99	59		T123	1
valid_sources[0x43]	25809	1			T23	1		T117	4		T133	2
valid_sources[0x44]	24075	1			T19	1		T8	1		T9	1
valid_sources[0x45]	24432	1			T1	2		T99	56		T118	2
valid_sources[0x46]	24435	1			T1	1		T99	53		T24	19
valid_sources[0x47]	24260	1			T21	1		T133	3		T99	39
valid_sources[0x48]	23595	1			T8	13		T23	1		T99	66
valid_sources[0x49]	25004	1			T21	1		T99	73		T118	1
valid_sources[0x4a]	24992	1			T23	1		T99	53		T206	1
valid_sources[0x4b]	24634	1			T143	5		T99	40		T28	1
valid_sources[0x4c]	24777	1			T19	1		T21	1		T4	2
valid_sources[0x4d]	26437	1			T19	1		T117	1		T99	56
valid_sources[0x4e]	25598	1			T9	2		T117	3		T133	2
valid_sources[0x4f]	25900	1			T19	1		T11	3		T23	1
valid_sources[0x50]	25927	1			T23	1		T143	1		T98	1
valid_sources[0x51]	30279	1			T1	3		T19	1		T11	1
valid_sources[0x52]	23122	1			T21	1		T99	65		T118	3
valid_sources[0x53]	23027	1			T3	1		T21	3		T99	61
valid_sources[0x54]	25288	1			T11	1		T23	1		T9	2
valid_sources[0x55]	25044	1			T117	1		T99	60		T123	4
valid_sources[0x56]	26033	1			T4	1		T133	8		T98	1
valid_sources[0x57]	25224	1			T19	1		T117	2		T99	51
valid_sources[0x58]	25315	1			T21	2		T117	1		T99	46
valid_sources[0x59]	25187	1			T99	68		T206	1		T123	1
valid_sources[0x5a]	25126	1			T99	52		T118	1		T123	1
valid_sources[0x5b]	24808	1			T99	65		T123	1		T100	8
valid_sources[0x5c]	25151	1			T3	1		T117	3		T99	56
valid_sources[0x5d]	24424	1			T1	1		T23	2		T9	3
valid_sources[0x5e]	25204	1			T117	1		T99	43		T28	1
valid_sources[0x5f]	25174	1			T23	1		T117	3		T116	29
valid_sources[0x60]	26638	1			T23	1		T99	49		T206	2
valid_sources[0x61]	24960	1			T23	1		T4	1		T99	58
valid_sources[0x62]	25190	1			T23	1		T9	1		T117	2
valid_sources[0x63]	25227	1			T117	2		T99	50		T118	1
valid_sources[0x64]	24511	1			T133	4		T99	56		T206	3
valid_sources[0x65]	26899	1			T1	1		T133	1		T99	53
valid_sources[0x66]	25147	1			T21	1		T9	1		T117	3
valid_sources[0x67]	25381	1			T21	2		T99	51		T118	2
valid_sources[0x68]	22850	1			T9	1		T99	75		T119	2
valid_sources[0x69]	25573	1			T99	44		T70	1		T123	4
valid_sources[0x6a]	24116	1			T1	1		T144	1		T117	1
valid_sources[0x6b]	23873	1			T19	1		T9	1		T133	5
valid_sources[0x6c]	25634	1			T117	1		T133	2		T99	61
valid_sources[0x6d]	23920	1			T1	2		T23	1		T10	6
valid_sources[0x6e]	24317	1			T19	1		T11	5		T144	2
valid_sources[0x6f]	23823	1			T144	1		T99	75		T123	1
valid_sources[0x70]	22935	1			T9	1		T99	50		T70	1
valid_sources[0x71]	23679	1			T23	1		T99	54		T118	3
valid_sources[0x72]	25346	1			T11	2		T23	1		T133	1
valid_sources[0x73]	25758	1			T21	2		T99	48		T206	1
valid_sources[0x74]	25279	1			T8	5		T22	1		T117	2
valid_sources[0x75]	25385	1			T11	7		T99	55		T118	1
valid_sources[0x76]	25050	1			T23	2		T99	40		T118	1
valid_sources[0x77]	23796	1			T21	1		T23	1		T117	1
valid_sources[0x78]	25464	1			T99	44		T123	2		T100	6
valid_sources[0x79]	24102	1			T4	1		T9	1		T143	1
valid_sources[0x7a]	23313	1			T19	1		T133	1		T99	84
valid_sources[0x7b]	25440	1			T23	1		T99	67		T119	6
valid_sources[0x7c]	24155	1			T1	1		T21	1		T9	1
valid_sources[0x7d]	24208	1			T21	2		T9	1		T99	64
valid_sources[0x7e]	24875	1			T1	2		T21	2		T116	5
valid_sources[0x7f]	24818	1			T21	2		T99	58		T206	1
valid_sources[0x80]	24520	1			T10	4		T99	64		T118	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1428649

1

T1

6

T2

6

T3

1

values[0x0]

all_enables

biggest_size

2121339

1

T1

14

T2

15

T3

4

values[0x1]

all_enables

biggest_size

2120727

1

T1

13

T2

15

T3

1