Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2926	1			T1	2		T2	1		T19	3
non_zero_bins[1]	2155	1			T1	1		T2	2		T8	2
zero	9216	1			T1	4		T2	1		T19	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	598	1			T2	1		T116	1		T99	8
uni	3992	1			T1	2		T2	1		T19	2
gen	4380	1			T1	2		T2	1		T19	1
res	894	1			T1	1		T8	2		T11	2
ins	4433	1			T1	2		T2	1		T19	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9680

1

T1

5

T2

1

T19

3

mubi_true

4617

1

T1

2

T2

3

T19

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

14297

1

T1

7

T2

4

T19

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	133	1			T99	2		T120	1		T113	1
upd	non_zero_bins[0]	pass	mubi_true	132	1			T99	2		T100	1		T113	2
upd	non_zero_bins[1]	pass	mubi_false	98	1			T99	1		T206	1		T113	1
upd	non_zero_bins[1]	pass	mubi_true	103	1			T2	1		T116	1		T99	1
upd	zero	pass	mubi_false	69	1			T99	1		T113	3		T147	1
upd	zero	pass	mubi_true	63	1			T99	1		T113	1		T162	1
uni	zero	pass	mubi_false	2957	1			T1	2		T2	1		T19	2
uni	zero	pass	mubi_true	1035	1			T21	1		T23	1		T143	1
gen	non_zero_bins[0]	pass	mubi_false	562	1			T8	3		T21	1		T11	13
gen	non_zero_bins[0]	pass	mubi_true	585	1			T1	1		T2	1		T19	1
gen	non_zero_bins[1]	pass	mubi_false	435	1			T144	3		T133	1		T99	4
gen	non_zero_bins[1]	pass	mubi_true	390	1			T144	1		T145	1		T99	3
gen	zero	pass	mubi_false	1967	1			T1	1		T8	1		T20	2
gen	zero	pass	mubi_true	441	1			T21	1		T27	1		T99	2
res	non_zero_bins[0]	pass	mubi_false	194	1			T11	2		T10	4		T117	2
res	non_zero_bins[0]	pass	mubi_true	207	1			T144	2		T99	1		T113	1
res	non_zero_bins[1]	pass	mubi_false	136	1			T1	1		T115	1		T119	2
res	non_zero_bins[1]	pass	mubi_true	168	1			T8	2		T9	2		T27	1
res	zero	pass	mubi_false	90	1			T10	2		T124	1		T165	3
res	zero	pass	mubi_true	99	1			T99	1		T118	2		T258	2
ins	non_zero_bins[0]	pass	mubi_false	544	1			T1	1		T19	1		T21	1
ins	non_zero_bins[0]	pass	mubi_true	569	1			T19	1		T8	1		T115	1
ins	non_zero_bins[1]	pass	mubi_false	427	1			T144	1		T99	3		T123	1
ins	non_zero_bins[1]	pass	mubi_true	398	1			T2	1		T23	1		T145	1
ins	zero	pass	mubi_false	2068	1			T21	1		T4	1		T143	1
ins	zero	pass	mubi_true	427	1			T1	1		T20	2		T21	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded