Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	100.00	94.44		78.38	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.09	100.00	94.44		78.38	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.09	100.00	94.44		78.38	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.11	100.00	94.44		78.38	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	41	3	3	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	46	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	3	3
43	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
76	1	1
77	1	1
80	1	1
81	1	1
			MISSING_ELSE
85	1	1
86	1	1
89	1	1
90	1	1
			MISSING_ELSE
94	1	1
97	1	1
98	1	1
			MISSING_ELSE
102	1	1
103	1	1
106	1	1
107	1	1
108	1	1
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
			MISSING_ELSE
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	1	1
136	1	1
137	1	1
139	1	1
144	1	1
145	1	1
146	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
171	1	1
174	1	1
182	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T22,T24
1	1	Covered	T1,T20,T21

 LINE       64
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T5,T6
1	1	Covered	T8,T11,T9

 LINE       182
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T25,T26
1	0	Covered	T3,T4,T5

 LINE       184
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T14,T25,T26
1	Covered	T3,T4,T5

 LINE       184
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T14,T25,T26
1	Not Covered

 LINE       184
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       198
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T22,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	58	78.38
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	152	Covered	T8,T11,T9
AutoCaptGenCnt	139	Covered	T8,T11,T9
AutoCaptReseedCnt	137	Covered	T8,T11,T9
AutoDispatch	121	Covered	T8,T11,T9
AutoFirstAckWait	115	Covered	T8,T11,T9
AutoLoadIns	67	Covered	T8,T11,T9
AutoSendGenCmd	146	Covered	T8,T11,T9
AutoSendReseedCmd	158	Covered	T8,T11,T9
BootDone	94	Covered	T1,T20,T21
BootGenAckWait	86	Covered	T1,T20,T21
BootInsAckWait	77	Covered	T1,T20,T21
BootLoadGen	81	Covered	T1,T20,T21
BootLoadIns	63	Covered	T1,T20,T21
BootLoadUni	98	Covered	T1,T21,T27
BootPulse	90	Covered	T1,T20,T21
BootUniAckWait	103	Covered	T1,T21,T27
Error	184	Covered	T3,T4,T5
Idle	108	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T14,T25,T26
SWPortMode	72	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	127	Covered	T8,T11,T9
AutoAckWait->Error	184	Not Covered
AutoAckWait->Idle	208	Covered	T10,T28,T29
AutoAckWait->RejectCsrngEntropy	184	Covered	T25,T26,T30
AutoCaptGenCnt->AutoSendGenCmd	146	Covered	T8,T11,T9
AutoCaptGenCnt->Error	184	Covered	T31
AutoCaptGenCnt->Idle	208	Covered	T32,T33,T34
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	158	Covered	T8,T11,T9
AutoCaptReseedCnt->Error	184	Covered	T35,T36,T37
AutoCaptReseedCnt->Idle	208	Covered	T38,T39,T40
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	139	Covered	T8,T11,T9
AutoDispatch->AutoCaptReseedCnt	137	Covered	T8,T11,T9
AutoDispatch->Error	184	Covered	T41,T42,T43
AutoDispatch->Idle	134	Covered	T8,T11,T9
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	121	Covered	T8,T11,T9
AutoFirstAckWait->Error	184	Covered	T6,T44,T45
AutoFirstAckWait->Idle	208	Covered	T46,T47,T48
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	115	Covered	T8,T11,T9
AutoLoadIns->Error	184	Covered	T49,T50,T51
AutoLoadIns->Idle	208	Covered	T5,T6,T7
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	152	Covered	T8,T11,T9
AutoSendGenCmd->Error	184	Covered	T52,T53,T54
AutoSendGenCmd->Idle	208	Covered	T10,T28,T55
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	164	Covered	T8,T11,T9
AutoSendReseedCmd->Error	184	Not Covered
AutoSendReseedCmd->Idle	208	Covered	T29,T56,T57
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	98	Covered	T1,T21,T27
BootDone->Error	184	Covered	T24,T58,T59
BootDone->Idle	208	Covered	T20,T60,T61
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	90	Covered	T1,T20,T21
BootGenAckWait->Error	184	Covered	T62
BootGenAckWait->Idle	208	Covered	T24,T63,T64
BootGenAckWait->RejectCsrngEntropy	184	Covered	T65,T66,T67
BootInsAckWait->BootLoadGen	81	Covered	T1,T20,T21
BootInsAckWait->Error	184	Covered	T63,T68,T69
BootInsAckWait->Idle	208	Covered	T70,T62,T71
BootInsAckWait->RejectCsrngEntropy	184	Covered	T72,T73,T74
BootLoadGen->BootGenAckWait	86	Covered	T1,T20,T21
BootLoadGen->Error	184	Covered	T75,T76,T77
BootLoadGen->Idle	208	Covered	T78,T79,T80
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	77	Covered	T1,T20,T21
BootLoadIns->Error	184	Covered	T78,T81,T82
BootLoadIns->Idle	208	Covered	T22,T83,T84
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	103	Covered	T1,T21,T27
BootLoadUni->Error	184	Covered	T85
BootLoadUni->Idle	208	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	94	Covered	T1,T20,T21
BootPulse->Error	184	Covered	T86
BootPulse->Idle	208	Covered	T87,T88,T89
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Covered	T90,T91
BootUniAckWait->Idle	108	Covered	T1,T21,T27
BootUniAckWait->RejectCsrngEntropy	184	Covered	T92,T93,T94
Idle->AutoLoadIns	67	Covered	T8,T11,T9
Idle->BootLoadIns	63	Covered	T1,T20,T21
Idle->Error	184	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	72	Covered	T1,T2,T3
RejectCsrngEntropy->Error	184	Covered	T14,T95,T96
RejectCsrngEntropy->Idle	208	Covered	T25,T26,T30
SWPortMode->Error	184	Covered	T3,T4,T97
SWPortMode->Idle	208	Covered	T98,T99,T100
SWPortMode->RejectCsrngEntropy	184	Covered	T14,T95,T101

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	41	2	2	100.00
CASE	60	35	35	100.00
IF	182	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if ((boot_req_mode_i && edn_enable_i))
-3-:	64	if ((auto_req_mode_i && edn_enable_i))
-4-:	68	if (edn_enable_i)
-5-:	80	if (csrng_cmd_ack_i)
-6-:	89	if (csrng_cmd_ack_i)
-7-:	97	if ((!boot_req_mode_i))
-8-:	106	if (csrng_cmd_ack_i)
-9-:	114	if (sw_cmd_req_load_i)
-10-:	120	if (csrng_cmd_ack_i)
-11-:	126	if (csrng_cmd_ack_i)
-12-:	132	if ((!auto_req_mode_i))
-13-:	136	if (max_reqs_cnt_zero_i)
-14-:	151	if (cmd_sent_i)
-15-:	163	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T11,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T21,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T20,T22,T24
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T21,T27
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T21,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T11,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T11,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T11,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T11,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T11,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T11,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T11,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T11,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T11,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T11,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T11,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T11,T9
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T11,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T11,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T11,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T25,T26
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T70

	LineNo.	Expression
-1-:	182	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	184	((state_q == Error)) ? 
-4-:	198	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T14,T25,T26
0	-	-	1	Covered	T20,T22,T10
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	217121993	145085	0	0
FpvSecCmErrorStEscalate_A	217121993	146256	0	0
u_state_regs_A	217088679	216908978	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	145085	0	0
T3	1181	634	0	0
T4	1243	558	0	0
T5	0	342	0	0
T6	0	362	0	0
T7	0	1020	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	362	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1111	0	0
T52	0	350	0	0
T70	0	280	0	0
T78	0	371	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	146256	0	0
T3	1181	635	0	0
T4	1243	559	0	0
T5	0	343	0	0
T6	0	363	0	0
T7	0	1021	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	363	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1112	0	0
T52	0	351	0	0
T70	0	281	0	0
T78	0	372	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217088679	216908978	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1017	853	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0