Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T108,T110,T154
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T98,T105,T112
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T8,T11,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433558494	599142	0	0
DepthKnown_A	434243986	433884584	0	0
RvalidKnown_A	434243986	433884584	0	0
WreadyKnown_A	434243986	433884584	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	433881800	680680	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433558494	599142	0	0
T4	762	0	0	0
T5	0	317	0	0
T6	0	85	0	0
T7	0	89	0	0
T8	10982	8378	0	0
T9	4234	1829	0	0
T10	0	4247	0	0
T11	4508	1602	0	0
T20	2802	0	0	0
T21	4472	0	0	0
T22	2174	0	0	0
T23	5472	0	0	0
T115	5726	0	0	0
T117	0	1400	0	0
T118	0	2272	0	0
T128	2374	0	0	0
T144	0	2661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434243986	433884584	0	0
T1	4680	4526	0	0
T2	2556	2366	0	0
T3	2362	2034	0	0
T8	10982	10836	0	0
T11	4508	4314	0	0
T19	4298	4190	0	0
T20	2802	2624	0	0
T21	4472	4342	0	0
T22	2174	2068	0	0
T23	5472	5274	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434243986	433884584	0	0
T1	4680	4526	0	0
T2	2556	2366	0	0
T3	2362	2034	0	0
T8	10982	10836	0	0
T11	4508	4314	0	0
T19	4298	4190	0	0
T20	2802	2624	0	0
T21	4472	4342	0	0
T22	2174	2068	0	0
T23	5472	5274	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434243986	433884584	0	0
T1	4680	4526	0	0
T2	2556	2366	0	0
T3	2362	2034	0	0
T8	10982	10836	0	0
T11	4508	4314	0	0
T19	4298	4190	0	0
T20	2802	2624	0	0
T21	4472	4342	0	0
T22	2174	2068	0	0
T23	5472	5274	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	433881800	680680	0	0
T3	2362	266	0	0
T4	2486	0	0	0
T5	0	1271	0	0
T6	0	694	0	0
T7	0	1604	0	0
T8	10982	8378	0	0
T9	4234	1829	0	0
T10	0	4247	0	0
T11	4508	1602	0	0
T19	4298	0	0	0
T20	2802	0	0	0
T21	4472	0	0	0
T22	2174	0	0	0
T23	5472	0	0	0
T117	0	1400	0	0
T144	0	2661	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T155,T33,T156
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T157
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T98,T105,T106
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T8,T11,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216779247	294137	0	0
DepthKnown_A	217121993	216942292	0	0
RvalidKnown_A	217121993	216942292	0	0
WreadyKnown_A	217121993	216942292	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216940900	334710	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216779247	294137	0	0
T4	381	0	0	0
T5	0	133	0	0
T6	0	33	0	0
T7	0	39	0	0
T8	5491	4192	0	0
T9	2117	905	0	0
T10	0	2027	0	0
T11	2254	783	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T115	2863	0	0	0
T117	0	664	0	0
T118	0	1095	0	0
T128	1187	0	0	0
T144	0	1324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216940900	334710	0	0
T3	1181	139	0	0
T4	1243	0	0	0
T5	0	583	0	0
T6	0	337	0	0
T7	0	789	0	0
T8	5491	4192	0	0
T9	2117	905	0	0
T10	0	2027	0	0
T11	2254	783	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T117	0	664	0	0
T144	0	1324	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T108,T110,T154
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T112,T158,T159
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T8,T11,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216779247	305005	0	0
DepthKnown_A	217121993	216942292	0	0
RvalidKnown_A	217121993	216942292	0	0
WreadyKnown_A	217121993	216942292	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216940900	345970	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216779247	305005	0	0
T4	381	0	0	0
T5	0	184	0	0
T6	0	52	0	0
T7	0	50	0	0
T8	5491	4186	0	0
T9	2117	924	0	0
T10	0	2220	0	0
T11	2254	819	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T115	2863	0	0	0
T117	0	736	0	0
T118	0	1177	0	0
T128	1187	0	0	0
T144	0	1337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216940900	345970	0	0
T3	1181	127	0	0
T4	1243	0	0	0
T5	0	688	0	0
T6	0	357	0	0
T7	0	815	0	0
T8	5491	4186	0	0
T9	2117	924	0	0
T10	0	2220	0	0
T11	2254	819	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T117	0	736	0	0
T144	0	1337	0	0