| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[0].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[1].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[2].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[3].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[4].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[5].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| push_pull_agent_pkg.uvm_test_top.env.m_endpoint_agent[6].cov::m_req_ack_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_req_ack | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1788 | 1 | T3 | 1 | T15 | 2 | T19 | 1 | ||||
| auto[2] | 26796 | 1 | T3 | 16 | T15 | 5 | T19 | 4 | ||||
| auto[3] | 25720 | 1 | T3 | 16 | T15 | 5 | T19 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 144 | 1 | T3 | 1 | T43 | 1 | T46 | 1 | ||||
| auto[2] | 5090 | 1 | T2 | 1 | T3 | 42 | T43 | 54 | ||||
| auto[3] | 5079 | 1 | T3 | 42 | T43 | 54 | T46 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 139 | 1 | T3 | 1 | T44 | 1 | T48 | 1 | ||||
| auto[2] | 5040 | 1 | T3 | 68 | T36 | 1 | T44 | 4 | ||||
| auto[3] | 5030 | 1 | T3 | 68 | T44 | 4 | T48 | 57 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 118 | 1 | T3 | 1 | T10 | 1 | T45 | 1 | ||||
| auto[2] | 4681 | 1 | T3 | 4 | T10 | 4 | T45 | 32 | ||||
| auto[3] | 4672 | 1 | T3 | 4 | T10 | 4 | T45 | 32 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 110 | 1 | T3 | 1 | T44 | 1 | T10 | 1 | ||||
| auto[2] | 3313 | 1 | T3 | 4 | T44 | 51 | T10 | 46 | ||||
| auto[3] | 3310 | 1 | T3 | 4 | T44 | 51 | T10 | 46 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 105 | 1 | T23 | 1 | T44 | 1 | T9 | 1 | ||||
| auto[2] | 4584 | 1 | T1 | 1 | T23 | 4 | T44 | 40 | ||||
| auto[3] | 4577 | 1 | T23 | 4 | T44 | 40 | T9 | 4 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | STATUS |
| ack_wo_req | 0 | Excluded |
| [auto[1]] | 0 | Excluded |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 103 | 1 | T44 | 1 | T10 | 1 | T11 | 1 | ||||
| auto[2] | 3605 | 1 | T44 | 44 | T10 | 38 | T11 | 4 | ||||
| auto[3] | 3601 | 1 | T44 | 44 | T10 | 38 | T11 | 4 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |