Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	662693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5342897

1

T1

10

T2

6

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1591154	1			T1	4		T2	5		T3	94
values[0x0]	2040884	1			T1	7		T2	6		T3	12
values[0x1]	2373552	1			T1	9		T2	4		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5676938

1

T1

11

T2

8

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23319	1			T19	6		T44	1		T55	4
valid_sources[0x01]	22374	1			T22	1		T55	6		T40	1215
valid_sources[0x02]	23412	1			T44	1		T55	3		T40	1276
valid_sources[0x03]	23376	1			T44	1		T55	3		T62	3
valid_sources[0x04]	22330	1			T19	1		T20	3		T55	2
valid_sources[0x05]	22897	1			T20	3		T55	4		T40	1134
valid_sources[0x06]	23851	1			T44	1		T55	3		T62	2
valid_sources[0x07]	22714	1			T40	1272		T162	1		T41	607
valid_sources[0x08]	23118	1			T15	1		T55	6		T40	1203
valid_sources[0x09]	23014	1			T48	3		T40	1216		T10	163
valid_sources[0x0a]	23304	1			T44	1		T62	1		T40	1250
valid_sources[0x0b]	23346	1			T55	10		T48	2		T40	1148
valid_sources[0x0c]	21938	1			T44	2		T55	2		T62	1
valid_sources[0x0d]	22021	1			T15	2		T22	7		T44	1
valid_sources[0x0e]	23582	1			T55	1		T40	1309		T162	1
valid_sources[0x0f]	23598	1			T20	2		T55	5		T40	1320
valid_sources[0x10]	23553	1			T55	5		T40	1220		T41	563
valid_sources[0x11]	23885	1			T55	5		T40	1210		T162	3
valid_sources[0x12]	23224	1			T44	2		T55	3		T40	1259
valid_sources[0x13]	23481	1			T55	6		T40	1248		T162	1
valid_sources[0x14]	24206	1			T44	1		T55	1		T40	1316
valid_sources[0x15]	25259	1			T15	1		T44	1		T55	1
valid_sources[0x16]	23422	1			T44	2		T55	4		T40	1288
valid_sources[0x17]	24458	1			T44	1		T55	4		T62	1
valid_sources[0x18]	22061	1			T55	2		T62	1		T48	1
valid_sources[0x19]	24102	1			T55	2		T40	1319		T45	3
valid_sources[0x1a]	22617	1			T55	3		T40	1181		T162	2
valid_sources[0x1b]	24850	1			T20	1		T55	1		T62	2
valid_sources[0x1c]	25425	1			T36	7		T44	1		T55	4
valid_sources[0x1d]	22607	1			T55	3		T62	1		T48	1
valid_sources[0x1e]	23553	1			T2	4		T55	1		T40	1315
valid_sources[0x1f]	23551	1			T2	6		T44	1		T55	1
valid_sources[0x20]	24655	1			T15	4		T19	2		T55	1
valid_sources[0x21]	25716	1			T44	1		T55	1		T48	1
valid_sources[0x22]	21548	1			T44	1		T55	1		T40	1234
valid_sources[0x23]	22714	1			T15	2		T55	5		T40	1152
valid_sources[0x24]	22798	1			T44	1		T55	1		T40	1190
valid_sources[0x25]	23860	1			T44	1		T55	5		T40	1207
valid_sources[0x26]	25731	1			T3	11		T55	1		T62	1
valid_sources[0x27]	24093	1			T55	2		T40	1225		T162	3
valid_sources[0x28]	25283	1			T19	10		T55	2		T40	1281
valid_sources[0x29]	23642	1			T55	1		T40	1258		T162	1
valid_sources[0x2a]	23293	1			T55	6		T62	1		T40	1273
valid_sources[0x2b]	21936	1			T2	2		T22	6		T44	1
valid_sources[0x2c]	23812	1			T15	1		T55	7		T48	2
valid_sources[0x2d]	24812	1			T44	1		T55	5		T40	1152
valid_sources[0x2e]	23551	1			T3	3		T20	1		T44	1
valid_sources[0x2f]	25316	1			T44	1		T55	2		T62	1
valid_sources[0x30]	23996	1			T55	2		T40	1224		T41	572
valid_sources[0x31]	23786	1			T15	1		T40	1303		T162	3
valid_sources[0x32]	24172	1			T44	2		T62	1		T40	1169
valid_sources[0x33]	24949	1			T55	4		T40	1199		T75	105
valid_sources[0x34]	22981	1			T55	3		T62	1		T40	1169
valid_sources[0x35]	23517	1			T55	5		T40	1323		T63	1
valid_sources[0x36]	24813	1			T62	1		T40	1254		T27	1
valid_sources[0x37]	23046	1			T55	1		T40	1223		T45	3
valid_sources[0x38]	23469	1			T44	1		T55	2		T40	1277
valid_sources[0x39]	23210	1			T44	1		T55	4		T62	3
valid_sources[0x3a]	23902	1			T19	2		T55	4		T40	1162
valid_sources[0x3b]	25104	1			T19	3		T44	1		T62	1
valid_sources[0x3c]	25377	1			T44	2		T55	6		T48	4
valid_sources[0x3d]	25394	1			T55	2		T48	1		T40	1234
valid_sources[0x3e]	22354	1			T55	4		T48	1		T40	1267
valid_sources[0x3f]	22570	1			T55	4		T62	2		T40	1264
valid_sources[0x40]	22976	1			T55	3		T40	1241		T45	7
valid_sources[0x41]	26278	1			T19	6		T55	5		T40	1173
valid_sources[0x42]	24089	1			T55	5		T40	1246		T63	4
valid_sources[0x43]	24072	1			T44	1		T55	4		T62	2
valid_sources[0x44]	23734	1			T44	1		T55	1		T40	1225
valid_sources[0x45]	24400	1			T44	1		T55	1		T48	2
valid_sources[0x46]	22938	1			T55	3		T40	1229		T162	1
valid_sources[0x47]	24720	1			T44	3		T55	1		T40	1192
valid_sources[0x48]	22008	1			T44	1		T55	1		T62	1
valid_sources[0x49]	23801	1			T22	1		T44	1		T55	3
valid_sources[0x4a]	25951	1			T15	1		T44	1		T55	5
valid_sources[0x4b]	22376	1			T44	1		T55	3		T40	1219
valid_sources[0x4c]	22915	1			T20	2		T14	16		T40	1178
valid_sources[0x4d]	22999	1			T55	1		T54	32		T40	1180
valid_sources[0x4e]	24161	1			T44	1		T55	2		T40	1242
valid_sources[0x4f]	21910	1			T55	2		T62	2		T40	1138
valid_sources[0x50]	24136	1			T44	1		T55	5		T48	7
valid_sources[0x51]	23260	1			T15	1		T55	4		T40	1234
valid_sources[0x52]	23025	1			T3	40		T55	1		T40	1218
valid_sources[0x53]	22934	1			T55	1		T62	2		T48	2
valid_sources[0x54]	21963	1			T22	1		T55	1		T40	1224
valid_sources[0x55]	23867	1			T20	6		T55	1		T40	1250
valid_sources[0x56]	25576	1			T3	6		T20	4		T55	1
valid_sources[0x57]	22233	1			T44	1		T55	2		T62	1
valid_sources[0x58]	24042	1			T19	2		T4	473		T44	1
valid_sources[0x59]	22890	1			T40	1178		T41	555		T161	1
valid_sources[0x5a]	22950	1			T55	1		T48	6		T40	1202
valid_sources[0x5b]	24700	1			T44	2		T55	2		T40	1185
valid_sources[0x5c]	24182	1			T44	1		T55	6		T40	1245
valid_sources[0x5d]	23438	1			T55	2		T40	1246		T45	7
valid_sources[0x5e]	24388	1			T55	1		T62	2		T40	1239
valid_sources[0x5f]	24672	1			T55	1		T40	1238		T27	1
valid_sources[0x60]	23197	1			T15	1		T40	1297		T63	3
valid_sources[0x61]	23456	1			T44	1		T55	6		T62	1
valid_sources[0x62]	22318	1			T20	5		T36	11		T44	1
valid_sources[0x63]	23627	1			T55	3		T40	1236		T45	1
valid_sources[0x64]	24487	1			T44	1		T55	1		T40	1321
valid_sources[0x65]	21741	1			T55	3		T62	6		T40	1245
valid_sources[0x66]	22887	1			T55	2		T48	1		T40	1209
valid_sources[0x67]	24069	1			T20	2		T44	1		T55	1
valid_sources[0x68]	24027	1			T55	2		T62	2		T40	1274
valid_sources[0x69]	23363	1			T15	1		T23	5		T44	1
valid_sources[0x6a]	23840	1			T44	1		T55	3		T62	1
valid_sources[0x6b]	25029	1			T40	1241		T63	1		T45	1
valid_sources[0x6c]	23075	1			T15	2		T20	3		T55	2
valid_sources[0x6d]	23714	1			T44	1		T55	4		T47	127
valid_sources[0x6e]	24121	1			T44	1		T55	8		T40	1231
valid_sources[0x6f]	23257	1			T55	4		T62	1		T48	4
valid_sources[0x70]	24167	1			T44	1		T55	2		T48	2
valid_sources[0x71]	24475	1			T15	1		T55	1		T40	1215
valid_sources[0x72]	23970	1			T44	2		T55	2		T40	1295
valid_sources[0x73]	23430	1			T55	6		T40	1264		T41	582
valid_sources[0x74]	22222	1			T55	2		T62	2		T48	1
valid_sources[0x75]	23617	1			T55	1		T62	3		T40	1228
valid_sources[0x76]	22935	1			T55	4		T40	1290		T27	1
valid_sources[0x77]	21670	1			T55	1		T62	2		T40	1227
valid_sources[0x78]	23371	1			T55	1		T48	1		T40	1150
valid_sources[0x79]	24556	1			T15	1		T55	2		T40	1248
valid_sources[0x7a]	22564	1			T55	4		T40	1177		T45	1
valid_sources[0x7b]	23463	1			T2	3		T19	4		T55	5
valid_sources[0x7c]	23798	1			T15	1		T55	1		T62	2
valid_sources[0x7d]	22836	1			T19	6		T20	2		T55	1
valid_sources[0x7e]	25758	1			T15	4		T55	2		T62	1
valid_sources[0x7f]	25335	1			T20	8		T44	1		T55	1
valid_sources[0x80]	23466	1			T22	1		T55	2		T62	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1347286

1

T1

2

T2

2

T3

4

values[0x0]

all_enables

biggest_size

1998299

1

T1

4

T2

3

T3

8

values[0x1]

all_enables

biggest_size

1997312

1

T1

4

T2

1

T3

9