Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2725	1			T3	3		T19	1		T8	1
non_zero_bins[1]	2093	1			T19	1		T8	6		T21	1
zero	8775	1			T1	6		T3	4		T15	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	549	1			T3	1		T19	1		T20	1
uni	3779	1			T1	1		T3	2		T19	1
gen	4176	1			T1	2		T3	2		T15	2
res	875	1			T8	2		T21	1		T43	1
ins	4214	1			T1	3		T3	2		T15	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9201

1

T1

4

T3

5

T15

1

mubi_true

4392

1

T1

2

T3

2

T15

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13593

1

T1

6

T3

7

T15

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	124	1			T3	1		T19	1		T20	1
upd	non_zero_bins[0]	pass	mubi_true	131	1			T4	1		T44	1		T55	1
upd	non_zero_bins[1]	pass	mubi_false	91	1			T55	1		T40	1		T41	1
upd	non_zero_bins[1]	pass	mubi_true	92	1			T62	1		T40	3		T41	3
upd	zero	pass	mubi_false	59	1			T40	1		T41	1		T198	1
upd	zero	pass	mubi_true	52	1			T41	2		T161	1		T86	1
uni	zero	pass	mubi_false	2816	1			T1	1		T3	2		T19	1
uni	zero	pass	mubi_true	963	1			T22	1		T52	1		T4	3
gen	non_zero_bins[0]	pass	mubi_false	491	1			T43	1		T40	12		T10	3
gen	non_zero_bins[0]	pass	mubi_true	521	1			T3	1		T20	1		T52	1
gen	non_zero_bins[1]	pass	mubi_false	439	1			T19	1		T21	1		T62	1
gen	non_zero_bins[1]	pass	mubi_true	393	1			T8	4		T4	2		T55	1
gen	zero	pass	mubi_false	1896	1			T1	1		T3	1		T20	1
gen	zero	pass	mubi_true	436	1			T1	1		T15	2		T21	1
res	non_zero_bins[0]	pass	mubi_false	194	1			T21	1		T43	1		T40	1
res	non_zero_bins[0]	pass	mubi_true	202	1			T4	1		T55	1		T40	3
res	non_zero_bins[1]	pass	mubi_false	137	1			T8	2		T4	1		T47	1
res	non_zero_bins[1]	pass	mubi_true	146	1			T40	2		T9	1		T41	4
res	zero	pass	mubi_false	100	1			T40	1		T27	1		T41	1
res	zero	pass	mubi_true	96	1			T40	3		T75	2		T41	1
ins	non_zero_bins[0]	pass	mubi_false	513	1			T3	1		T44	1		T55	1
ins	non_zero_bins[0]	pass	mubi_true	549	1			T8	1		T21	1		T52	1
ins	non_zero_bins[1]	pass	mubi_false	378	1			T52	1		T43	1		T4	2
ins	non_zero_bins[1]	pass	mubi_true	417	1			T62	1		T40	8		T45	1
ins	zero	pass	mubi_false	1963	1			T1	2		T15	1		T19	1
ins	zero	pass	mubi_true	394	1			T1	1		T3	1		T15	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded