Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.63	100.00	94.44		81.08	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.65	100.00	94.44		81.08	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	41	3	3	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	46	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	3	3
43	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
76	1	1
77	1	1
80	1	1
81	1	1
			MISSING_ELSE
85	1	1
86	1	1
89	1	1
90	1	1
			MISSING_ELSE
94	1	1
97	1	1
98	1	1
			MISSING_ELSE
102	1	1
103	1	1
106	1	1
107	1	1
108	1	1
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
			MISSING_ELSE
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	1	1
136	1	1
137	1	1
139	1	1
144	1	1
145	1	1
146	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
171	1	1
174	1	1
182	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T23,T36
1	1	Covered	T1,T3,T15

 LINE       64
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T15,T9,T5
1	1	Covered	T8,T9,T10

 LINE       182
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T27,T29
1	0	Covered	T1,T2,T36

 LINE       184
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T15,T27,T29
1	Covered	T1,T2,T36

 LINE       184
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T15,T27,T29
1	Not Covered

 LINE       184
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T36

 LINE       198
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T23

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	60	81.08
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	152	Covered	T8,T9,T10
AutoCaptGenCnt	139	Covered	T8,T9,T10
AutoCaptReseedCnt	137	Covered	T8,T9,T10
AutoDispatch	121	Covered	T8,T9,T10
AutoFirstAckWait	115	Covered	T8,T9,T10
AutoLoadIns	67	Covered	T8,T9,T10
AutoSendGenCmd	146	Covered	T8,T9,T10
AutoSendReseedCmd	158	Covered	T8,T9,T10
BootDone	94	Covered	T1,T3,T20
BootGenAckWait	86	Covered	T1,T3,T20
BootInsAckWait	77	Covered	T1,T3,T15
BootLoadGen	81	Covered	T1,T3,T20
BootLoadIns	63	Covered	T1,T3,T15
BootLoadUni	98	Covered	T1,T3,T20
BootPulse	90	Covered	T1,T3,T20
BootUniAckWait	103	Covered	T1,T3,T20
Error	184	Covered	T1,T2,T36
Idle	108	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T15,T27,T29
SWPortMode	72	Covered	T2,T3,T15

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	127	Covered	T8,T9,T10
AutoAckWait->Error	184	Covered	T56,T95,T96
AutoAckWait->Idle	208	Covered	T9,T75,T78
AutoAckWait->RejectCsrngEntropy	184	Covered	T27,T28,T97
AutoCaptGenCnt->AutoSendGenCmd	146	Covered	T8,T9,T10
AutoCaptGenCnt->Error	184	Covered	T6,T67,T98
AutoCaptGenCnt->Idle	208	Covered	T99,T100,T101
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	158	Covered	T8,T9,T10
AutoCaptReseedCnt->Error	184	Covered	T102,T103,T104
AutoCaptReseedCnt->Idle	208	Covered	T105,T106,T107
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	139	Covered	T8,T9,T10
AutoDispatch->AutoCaptReseedCnt	137	Covered	T8,T9,T10
AutoDispatch->Error	184	Covered	T108,T109,T110
AutoDispatch->Idle	134	Covered	T8,T10,T11
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	121	Covered	T8,T9,T10
AutoFirstAckWait->Error	184	Covered	T5,T111,T112
AutoFirstAckWait->Idle	208	Covered	T78,T113,T114
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	115	Covered	T8,T9,T10
AutoLoadIns->Error	184	Covered	T7,T115,T116
AutoLoadIns->Idle	208	Covered	T9,T5,T6
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	152	Covered	T8,T9,T10
AutoSendGenCmd->Error	184	Covered	T81,T117,T118
AutoSendGenCmd->Idle	208	Covered	T119,T120,T121
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	164	Covered	T8,T9,T10
AutoSendReseedCmd->Error	184	Covered	T122,T59,T123
AutoSendReseedCmd->Idle	208	Covered	T75,T88,T124
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	98	Covered	T1,T3,T20
BootDone->Error	184	Covered	T125,T126
BootDone->Idle	208	Covered	T23,T46,T127
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	90	Covered	T1,T3,T20
BootGenAckWait->Error	184	Covered	T128,T129,T130
BootGenAckWait->Idle	208	Covered	T125,T131,T90
BootGenAckWait->RejectCsrngEntropy	184	Covered	T69
BootInsAckWait->BootLoadGen	81	Covered	T1,T3,T20
BootInsAckWait->Error	184	Covered	T132,T133,T134
BootInsAckWait->Idle	208	Covered	T1,T36,T14
BootInsAckWait->RejectCsrngEntropy	184	Covered	T15,T135,T136
BootLoadGen->BootGenAckWait	86	Covered	T1,T3,T20
BootLoadGen->Error	184	Covered	T36
BootLoadGen->Idle	208	Covered	T137,T138,T139
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	77	Covered	T1,T3,T15
BootLoadIns->Error	184	Covered	T14,T140,T141
BootLoadIns->Idle	208	Covered	T84,T142,T143
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	103	Covered	T1,T3,T20
BootLoadUni->Error	184	Covered	T80,T58,T144
BootLoadUni->Idle	208	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	94	Covered	T1,T3,T20
BootPulse->Error	184	Covered	T145,T146,T147
BootPulse->Idle	208	Covered	T93,T148,T149
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Covered	T61,T150,T151
BootUniAckWait->Idle	108	Covered	T3,T20,T21
BootUniAckWait->RejectCsrngEntropy	184	Covered	T53,T152,T153
Idle->AutoLoadIns	67	Covered	T8,T9,T10
Idle->BootLoadIns	63	Covered	T1,T3,T15
Idle->Error	184	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	72	Covered	T2,T3,T15
RejectCsrngEntropy->Error	184	Covered	T60
RejectCsrngEntropy->Idle	208	Covered	T15,T27,T28
SWPortMode->Error	184	Covered	T57,T154,T49
SWPortMode->Idle	208	Covered	T15,T4,T55
SWPortMode->RejectCsrngEntropy	184	Covered	T29,T155,T60

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	41	2	2	100.00
CASE	60	35	35	100.00
IF	182	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if ((boot_req_mode_i && edn_enable_i))
-3-:	64	if ((auto_req_mode_i && edn_enable_i))
-4-:	68	if (edn_enable_i)
-5-:	80	if (csrng_cmd_ack_i)
-6-:	89	if (csrng_cmd_ack_i)
-7-:	97	if ((!boot_req_mode_i))
-8-:	106	if (csrng_cmd_ack_i)
-9-:	114	if (sw_cmd_req_load_i)
-10-:	120	if (csrng_cmd_ack_i)
-11-:	126	if (csrng_cmd_ack_i)
-12-:	132	if ((!auto_req_mode_i))
-13-:	136	if (max_reqs_cnt_zero_i)
-14-:	151	if (cmd_sent_i)
-15-:	163	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T15
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T23,T36
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T20,T21
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T20
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T8,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T10
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T27,T29
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T36
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T29

	LineNo.	Expression
-1-:	182	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	184	((state_q == Error)) ? 
-4-:	198	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T36
1	0	1	-	Not Covered
1	0	0	-	Covered	T15,T27,T29
0	-	-	1	Covered	T1,T15,T23
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	213976727	144143	0	0
FpvSecCmErrorStEscalate_A	213976727	145309	0	0
u_state_regs_A	213942878	213764127	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	144143	0	0
T1	1228	606	0	0
T2	1958	1109	0	0
T3	3569	0	0	0
T5	0	1080	0	0
T6	0	614	0	0
T7	0	411	0	0
T8	4440	0	0	0
T14	0	352	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1044	0	0
T36	0	627	0	0
T80	0	320	0	0
T81	0	1110	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	145309	0	0
T1	1228	607	0	0
T2	1958	1110	0	0
T3	3569	0	0	0
T5	0	1081	0	0
T6	0	615	0	0
T7	0	412	0	0
T8	4440	0	0	0
T14	0	353	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1045	0	0
T36	0	628	0	0
T80	0	321	0	0
T81	0	1111	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213942878	213764127	0	0
T1	1005	874	0	0
T2	1771	1587	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0