Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T37,T38
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T39,T32
1	0	1	Covered	T1,T2,T15
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	427233924	606131	0	0
DepthKnown_A	427953454	427595952	0	0
RvalidKnown_A	427953454	427595952	0	0
WreadyKnown_A	427953454	427595952	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	427590484	693335	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427233924	606131	0	0
T4	24464	0	0	0
T5	0	81	0	0
T6	0	293	0	0
T8	8880	2822	0	0
T9	0	3046	0	0
T10	0	4229	0	0
T11	0	2507	0	0
T15	4970	207	0	0
T19	4968	0	0	0
T20	3744	0	0	0
T21	4012	0	0	0
T22	2666	0	0	0
T23	2190	0	0	0
T27	0	795	0	0
T43	6410	0	0	0
T52	4004	0	0	0
T75	0	5941	0	0
T78	0	3891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427953454	427595952	0	0
T1	2456	2194	0	0
T2	3916	3548	0	0
T3	7138	6990	0	0
T8	8880	8686	0	0
T15	4970	4812	0	0
T19	4968	4860	0	0
T20	3744	3640	0	0
T21	4012	3862	0	0
T22	2666	2554	0	0
T23	2190	2082	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427953454	427595952	0	0
T1	2456	2194	0	0
T2	3916	3548	0	0
T3	7138	6990	0	0
T8	8880	8686	0	0
T15	4970	4812	0	0
T19	4968	4860	0	0
T20	3744	3640	0	0
T21	4012	3862	0	0
T22	2666	2554	0	0
T23	2190	2082	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427953454	427595952	0	0
T1	2456	2194	0	0
T2	3916	3548	0	0
T3	7138	6990	0	0
T8	8880	8686	0	0
T15	4970	4812	0	0
T19	4968	4860	0	0
T20	3744	3640	0	0
T21	4012	3862	0	0
T22	2666	2554	0	0
T23	2190	2082	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	427590484	693335	0	0
T1	2456	304	0	0
T2	3916	288	0	0
T3	7138	0	0	0
T5	0	1538	0	0
T8	8880	2822	0	0
T9	0	3046	0	0
T10	0	4229	0	0
T14	0	220	0	0
T15	4970	207	0	0
T19	4968	0	0	0
T20	3744	0	0	0
T21	4012	0	0	0
T22	2666	0	0	0
T23	2190	0	0	0
T36	0	266	0	0
T75	0	5941	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T156,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T157
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T32,T158
1	0	1	Covered	T1,T2,T15
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	213616962	296980	0	0
DepthKnown_A	213976727	213797976	0	0
RvalidKnown_A	213976727	213797976	0	0
WreadyKnown_A	213976727	213797976	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	213795242	340207	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213616962	296980	0	0
T4	12232	0	0	0
T5	0	37	0	0
T6	0	115	0	0
T8	4440	1413	0	0
T9	0	1509	0	0
T10	0	2091	0	0
T11	0	1237	0	0
T15	2485	37	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T27	0	404	0	0
T43	3205	0	0	0
T52	2002	0	0	0
T75	0	2844	0	0
T78	0	1931	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	213795242	340207	0	0
T1	1228	155	0	0
T2	1958	148	0	0
T3	3569	0	0	0
T5	0	755	0	0
T8	4440	1413	0	0
T9	0	1509	0	0
T10	0	2091	0	0
T14	0	111	0	0
T15	2485	37	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T36	0	136	0	0
T75	0	2844	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T37,T38
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T159,T160
1	0	1	Covered	T1,T2,T15
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	213616962	309151	0	0
DepthKnown_A	213976727	213797976	0	0
RvalidKnown_A	213976727	213797976	0	0
WreadyKnown_A	213976727	213797976	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	213795242	353128	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213616962	309151	0	0
T4	12232	0	0	0
T5	0	44	0	0
T6	0	178	0	0
T8	4440	1409	0	0
T9	0	1537	0	0
T10	0	2138	0	0
T11	0	1270	0	0
T15	2485	170	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T27	0	391	0	0
T43	3205	0	0	0
T52	2002	0	0	0
T75	0	3097	0	0
T78	0	1960	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	213795242	353128	0	0
T1	1228	149	0	0
T2	1958	140	0	0
T3	3569	0	0	0
T5	0	783	0	0
T8	4440	1409	0	0
T9	0	1537	0	0
T10	0	2138	0	0
T14	0	109	0	0
T15	2485	170	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T36	0	130	0	0
T75	0	3097	0	0