Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2521	1			T1	2		T22	2		T9	7
non_zero_bins[1]	1725	1			T3	3		T22	1		T10	6
zero	7721	1			T1	2		T2	4		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	476	1			T22	1		T23	1		T38	7
uni	3272	1			T1	1		T3	2		T22	1
gen	3682	1			T1	1		T2	1		T3	2
res	808	1			T1	1		T3	1		T9	2
ins	3729	1			T1	1		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8057

1

T1

2

T2

3

T3

5

mubi_true

3910

1

T1

2

T2

1

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

11967

1

T1

4

T2

4

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	104	1			T39	2		T78	2		T205	3
upd	non_zero_bins[0]	pass	mubi_true	117	1			T22	1		T23	1		T38	2
upd	non_zero_bins[1]	pass	mubi_false	71	1			T79	1		T39	2		T53	2
upd	non_zero_bins[1]	pass	mubi_true	94	1			T38	3		T39	3		T40	4
upd	zero	pass	mubi_false	46	1			T38	1		T39	1		T40	1
upd	zero	pass	mubi_true	44	1			T38	1		T39	1		T53	1
uni	zero	pass	mubi_false	2424	1			T1	1		T3	2		T22	1
uni	zero	pass	mubi_true	848	1			T38	19		T39	14		T53	7
gen	non_zero_bins[0]	pass	mubi_false	489	1			T22	1		T10	1		T38	5
gen	non_zero_bins[0]	pass	mubi_true	467	1			T1	1		T9	4		T38	6
gen	non_zero_bins[1]	pass	mubi_false	345	1			T10	5		T38	4		T39	2
gen	non_zero_bins[1]	pass	mubi_true	304	1			T3	1		T38	5		T39	7
gen	zero	pass	mubi_false	1640	1			T2	1		T3	1		T4	1
gen	zero	pass	mubi_true	437	1			T23	1		T4	1		T38	2
res	non_zero_bins[0]	pass	mubi_false	191	1			T9	2		T38	1		T39	3
res	non_zero_bins[0]	pass	mubi_true	187	1			T1	1		T38	3		T39	2
res	non_zero_bins[1]	pass	mubi_false	124	1			T38	1		T39	2		T47	1
res	non_zero_bins[1]	pass	mubi_true	129	1			T3	1		T39	3		T40	2
res	zero	pass	mubi_false	97	1			T10	2		T38	1		T39	2
res	zero	pass	mubi_true	80	1			T21	2		T60	1		T40	2
ins	non_zero_bins[0]	pass	mubi_false	499	1			T9	1		T38	14		T79	1
ins	non_zero_bins[0]	pass	mubi_true	467	1			T38	7		T39	7		T21	1
ins	non_zero_bins[1]	pass	mubi_false	311	1			T3	1		T10	1		T38	3
ins	non_zero_bins[1]	pass	mubi_true	347	1			T22	1		T38	8		T39	8
ins	zero	pass	mubi_false	1716	1			T1	1		T2	2		T3	1
ins	zero	pass	mubi_true	389	1			T2	1		T23	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded