Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	642827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5254872

1

T1

34

T2

4

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1559786	1			T1	53		T2	1		T3	35
values[0x0]	2005647	1			T1	19		T2	10		T3	30
values[0x1]	2332266	1			T1	11		T2	13		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	317690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5580009

1

T1

51

T2

8

T3

63

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21401	1			T4	351		T119	2		T117	470
valid_sources[0x01]	22382	1			T4	426		T103	9		T121	3
valid_sources[0x02]	23481	1			T3	3		T4	426		T6	4
valid_sources[0x03]	24202	1			T3	1		T4	368		T6	8
valid_sources[0x04]	22403	1			T4	350		T6	2		T121	1
valid_sources[0x05]	22711	1			T4	370		T11	8		T28	1
valid_sources[0x06]	22668	1			T4	415		T121	5		T119	1
valid_sources[0x07]	24017	1			T4	413		T6	10		T119	1
valid_sources[0x08]	24118	1			T4	412		T117	7		T149	1
valid_sources[0x09]	24634	1			T4	368		T121	6		T119	1
valid_sources[0x0a]	22053	1			T4	331		T119	2		T117	94
valid_sources[0x0b]	22282	1			T4	423		T103	13		T117	1
valid_sources[0x0c]	23605	1			T4	389		T6	4		T106	1
valid_sources[0x0d]	23992	1			T1	1		T4	366		T6	1
valid_sources[0x0e]	23726	1			T4	401		T6	1		T11	13
valid_sources[0x0f]	22763	1			T4	342		T6	4		T106	7
valid_sources[0x10]	25265	1			T1	5		T4	367		T28	1
valid_sources[0x11]	25257	1			T4	376		T6	2		T117	233
valid_sources[0x12]	22497	1			T3	1		T4	386		T6	2
valid_sources[0x13]	24589	1			T4	377		T6	1		T21	1
valid_sources[0x14]	21394	1			T4	440		T6	4		T20	1
valid_sources[0x15]	24225	1			T2	4		T4	367		T6	2
valid_sources[0x16]	23508	1			T4	360		T6	1		T117	125
valid_sources[0x17]	22571	1			T3	1		T4	332		T106	4
valid_sources[0x18]	22361	1			T4	357		T103	5		T117	902
valid_sources[0x19]	23881	1			T1	1		T4	396		T6	5
valid_sources[0x1a]	22462	1			T4	435		T6	3		T103	5
valid_sources[0x1b]	24118	1			T4	375		T6	2		T117	3
valid_sources[0x1c]	22401	1			T4	361		T6	2		T103	3
valid_sources[0x1d]	22069	1			T4	407		T6	1		T86	1
valid_sources[0x1e]	24142	1			T3	1		T4	384		T6	1
valid_sources[0x1f]	22015	1			T1	2		T4	328		T6	7
valid_sources[0x20]	22578	1			T4	343		T121	4		T17	3
valid_sources[0x21]	21674	1			T3	2		T4	374		T6	4
valid_sources[0x22]	23858	1			T3	2		T4	341		T6	5
valid_sources[0x23]	24517	1			T4	299		T103	8		T28	1
valid_sources[0x24]	23568	1			T1	1		T4	366		T103	10
valid_sources[0x25]	22541	1			T3	1		T4	405		T6	5
valid_sources[0x26]	22881	1			T4	409		T6	2		T121	1
valid_sources[0x27]	23589	1			T1	1		T4	346		T6	4
valid_sources[0x28]	22288	1			T4	309		T6	4		T117	14
valid_sources[0x29]	23840	1			T1	1		T4	327		T119	4
valid_sources[0x2a]	23611	1			T4	395		T6	7		T119	2
valid_sources[0x2b]	22866	1			T4	430		T6	1		T121	1
valid_sources[0x2c]	22323	1			T4	370		T6	2		T103	17
valid_sources[0x2d]	22659	1			T4	386		T6	11		T21	1
valid_sources[0x2e]	22475	1			T4	345		T6	4		T20	2
valid_sources[0x2f]	22686	1			T4	393		T6	6		T103	3
valid_sources[0x30]	22807	1			T4	380		T6	4		T106	1
valid_sources[0x31]	22613	1			T3	2		T4	419		T20	5
valid_sources[0x32]	21680	1			T4	432		T6	1		T21	1
valid_sources[0x33]	21648	1			T2	2		T4	331		T119	2
valid_sources[0x34]	22796	1			T4	374		T6	2		T121	3
valid_sources[0x35]	22324	1			T4	409		T6	2		T121	1
valid_sources[0x36]	23170	1			T1	2		T4	380		T6	3
valid_sources[0x37]	22291	1			T3	3		T4	385		T6	3
valid_sources[0x38]	26209	1			T4	367		T6	4		T21	1
valid_sources[0x39]	23297	1			T3	1		T4	354		T6	3
valid_sources[0x3a]	24751	1			T3	1		T4	264		T6	4
valid_sources[0x3b]	23119	1			T1	1		T3	1		T4	376
valid_sources[0x3c]	22961	1			T4	398		T6	5		T28	1
valid_sources[0x3d]	22466	1			T2	2		T4	344		T6	3
valid_sources[0x3e]	23897	1			T4	376		T6	2		T20	2
valid_sources[0x3f]	22762	1			T4	359		T6	9		T28	1
valid_sources[0x40]	22567	1			T4	373		T103	3		T117	138
valid_sources[0x41]	23925	1			T3	1		T4	325		T6	5
valid_sources[0x42]	22326	1			T3	1		T4	423		T6	2
valid_sources[0x43]	22373	1			T4	346		T6	4		T11	3
valid_sources[0x44]	22128	1			T4	322		T6	4		T119	2
valid_sources[0x45]	22451	1			T3	1		T4	384		T6	2
valid_sources[0x46]	23322	1			T4	450		T6	2		T121	1
valid_sources[0x47]	23679	1			T4	379		T6	5		T121	1
valid_sources[0x48]	22313	1			T1	1		T4	391		T6	1
valid_sources[0x49]	22643	1			T4	331		T6	1		T106	3
valid_sources[0x4a]	22183	1			T3	1		T4	388		T6	2
valid_sources[0x4b]	22015	1			T1	1		T2	1		T3	1
valid_sources[0x4c]	22788	1			T4	340		T6	6		T121	5
valid_sources[0x4d]	23561	1			T4	335		T6	2		T28	1
valid_sources[0x4e]	23905	1			T1	3		T4	464		T6	1
valid_sources[0x4f]	23158	1			T4	373		T121	2		T119	1
valid_sources[0x50]	22853	1			T4	390		T6	1		T103	1
valid_sources[0x51]	24833	1			T4	461		T6	3		T119	2
valid_sources[0x52]	22504	1			T4	351		T28	1		T117	441
valid_sources[0x53]	23403	1			T4	394		T6	8		T28	1
valid_sources[0x54]	21682	1			T4	378		T6	3		T121	14
valid_sources[0x55]	23051	1			T4	352		T6	4		T103	29
valid_sources[0x56]	22906	1			T3	2		T4	392		T119	2
valid_sources[0x57]	21794	1			T1	1		T4	332		T117	405
valid_sources[0x58]	23270	1			T4	333		T6	5		T121	10
valid_sources[0x59]	21798	1			T3	2		T4	335		T6	1
valid_sources[0x5a]	24859	1			T3	2		T4	368		T11	8
valid_sources[0x5b]	21654	1			T4	441		T28	2		T119	1
valid_sources[0x5c]	23848	1			T4	396		T6	1		T103	28
valid_sources[0x5d]	22720	1			T1	5		T4	328		T6	2
valid_sources[0x5e]	23133	1			T4	391		T119	3		T117	322
valid_sources[0x5f]	23837	1			T4	353		T11	1		T121	9
valid_sources[0x60]	23335	1			T3	1		T4	354		T6	1
valid_sources[0x61]	23161	1			T1	5		T4	357		T119	2
valid_sources[0x62]	22376	1			T4	313		T6	2		T10	19
valid_sources[0x63]	23689	1			T1	1		T3	2		T4	399
valid_sources[0x64]	22627	1			T4	378		T6	3		T119	1
valid_sources[0x65]	23417	1			T3	2		T4	394		T6	2
valid_sources[0x66]	22579	1			T3	2		T4	357		T6	1
valid_sources[0x67]	22229	1			T4	386		T105	5		T121	2
valid_sources[0x68]	25274	1			T4	396		T6	3		T119	3
valid_sources[0x69]	22175	1			T4	363		T6	2		T119	1
valid_sources[0x6a]	24441	1			T4	340		T6	9		T103	4
valid_sources[0x6b]	23847	1			T4	381		T6	2		T119	1
valid_sources[0x6c]	23606	1			T4	397		T6	11		T21	1
valid_sources[0x6d]	22900	1			T3	1		T4	364		T6	1
valid_sources[0x6e]	22909	1			T1	3		T4	309		T6	3
valid_sources[0x6f]	22588	1			T2	1		T4	365		T28	1
valid_sources[0x70]	23196	1			T4	386		T6	1		T21	1
valid_sources[0x71]	23394	1			T4	399		T6	9		T119	1
valid_sources[0x72]	22430	1			T4	374		T6	1		T21	1
valid_sources[0x73]	23646	1			T4	364		T6	1		T21	3
valid_sources[0x74]	24179	1			T1	3		T2	1		T4	408
valid_sources[0x75]	23312	1			T4	320		T6	1		T121	2
valid_sources[0x76]	24388	1			T4	390		T6	7		T21	1
valid_sources[0x77]	23181	1			T1	2		T4	413		T6	3
valid_sources[0x78]	23065	1			T4	379		T28	1		T117	181
valid_sources[0x79]	22535	1			T3	1		T4	380		T6	1
valid_sources[0x7a]	22973	1			T1	1		T3	2		T4	408
valid_sources[0x7b]	22699	1			T4	415		T106	4		T121	5
valid_sources[0x7c]	22595	1			T3	1		T4	366		T6	4
valid_sources[0x7d]	24319	1			T4	330		T119	2		T117	55
valid_sources[0x7e]	23054	1			T4	302		T119	1		T117	57
valid_sources[0x7f]	22782	1			T4	355		T23	6		T121	1
valid_sources[0x80]	22729	1			T4	366		T25	3		T118	111

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1326992

1

T1

7

T2

1

T3

2

values[0x0]

all_enables

biggest_size

1964070

1

T1

18

T2

1

T3

29

values[0x1]

all_enables

biggest_size

1963810

1

T1

9

T2

2

T3

19