Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2606	1			T3	7		T4	25		T19	1
non_zero_bins[1]	1987	1			T1	2		T4	23		T19	1
zero	8874	1			T1	3		T3	1		T4	111

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	528	1			T4	7		T103	1		T120	1
uni	3795	1			T1	2		T3	1		T4	52
gen	4070	1			T1	1		T3	4		T4	43
res	821	1			T3	2		T4	5		T19	1
ins	4253	1			T1	2		T3	1		T4	52

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9152

1

T1

2

T3

7

T4

117

mubi_true

4315

1

T1

3

T3

1

T4

42

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13467

1

T1

5

T3

8

T4

159

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	137	1			T117	1		T118	2		T196	1
upd	non_zero_bins[0]	pass	mubi_true	114	1			T4	4		T103	1		T196	1
upd	non_zero_bins[1]	pass	mubi_false	96	1			T4	2		T120	1		T151	1
upd	non_zero_bins[1]	pass	mubi_true	90	1			T4	1		T28	1		T119	1
upd	zero	pass	mubi_false	38	1			T147	1		T150	2		T236	1
upd	zero	pass	mubi_true	53	1			T118	1		T123	1		T237	1
uni	zero	pass	mubi_false	2775	1			T1	1		T3	1		T4	39
uni	zero	pass	mubi_true	1020	1			T1	1		T4	13		T103	5
gen	non_zero_bins[0]	pass	mubi_false	490	1			T3	4		T4	4		T11	8
gen	non_zero_bins[0]	pass	mubi_true	453	1			T4	5		T19	1		T117	6
gen	non_zero_bins[1]	pass	mubi_false	404	1			T4	6		T103	1		T120	1
gen	non_zero_bins[1]	pass	mubi_true	354	1			T1	1		T4	3		T131	1
gen	zero	pass	mubi_false	1927	1			T4	25		T5	1		T20	2
gen	zero	pass	mubi_true	442	1			T20	2		T24	1		T23	2
res	non_zero_bins[0]	pass	mubi_false	187	1			T3	2		T4	1		T103	1
res	non_zero_bins[0]	pass	mubi_true	197	1			T4	1		T103	3		T117	3
res	non_zero_bins[1]	pass	mubi_false	119	1			T4	1		T10	1		T56	1
res	non_zero_bins[1]	pass	mubi_true	127	1			T117	1		T118	1		T13	2
res	zero	pass	mubi_false	107	1			T4	1		T27	1		T238	1
res	zero	pass	mubi_true	84	1			T4	1		T19	1		T11	2
ins	non_zero_bins[0]	pass	mubi_false	521	1			T4	3		T11	1		T103	1
ins	non_zero_bins[0]	pass	mubi_true	507	1			T3	1		T4	7		T103	2
ins	non_zero_bins[1]	pass	mubi_false	399	1			T1	1		T4	8		T19	1
ins	non_zero_bins[1]	pass	mubi_true	398	1			T4	2		T103	1		T121	1
ins	zero	pass	mubi_false	1952	1			T4	27		T5	1		T20	2
ins	zero	pass	mubi_true	476	1			T1	1		T4	5		T20	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded