Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T4
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94,T95
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T4
DataWait->AckPls	80	Covered	T1,T3,T4
DataWait->Disabled	107	Covered	T117,T82,T17
DataWait->Error	99	Covered	T14,T7,T8
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T3,T4
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T3,T4
DataWait	-	-	-	0	Covered	T1,T3,T4
AckPls	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T5,T6,T76

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1557286486	978941	0	0
FpvSecCmErrorStEscalate_A	1557286486	986214	0	0
u_state_regs_A	1557252635	1556094359	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557286486	978941	0	0
T5	3493	1336	0	0
T6	317954	120330	0	0
T7	0	7644	0	0
T8	0	2814	0	0
T9	0	4200	0	0
T10	24948	0	0	0
T11	18571	0	0	0
T14	7259	4214	0	0
T19	16219	0	0	0
T20	13888	0	0	0
T21	9975	0	0	0
T24	5789	0	0	0
T75	0	4214	0	0
T76	0	2400	0	0
T102	0	4214	0	0
T105	0	7791	0	0
T106	11298	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557286486	986214	0	0
T5	3493	1343	0	0
T6	317954	122150	0	0
T7	0	7651	0	0
T8	0	2821	0	0
T9	0	4207	0	0
T10	24948	0	0	0
T11	18571	0	0	0
T14	7259	4221	0	0
T19	16219	0	0	0
T20	13888	0	0	0
T21	9975	0	0	0
T24	5789	0	0	0
T75	0	4221	0	0
T76	0	2407	0	0
T102	0	4221	0	0
T105	0	7798	0	0
T106	11298	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1557252635	1556094359	0	0
T1	22078	21609	0	0
T2	6503	6118	0	0
T3	30366	29960	0	0
T4	3202605	3202514	0	0
T5	3381	2380	0	0
T6	317954	166838	0	0
T10	24948	24255	0	0
T19	16219	15673	0	0
T20	13888	13384	0	0
T21	9975	9541	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T4
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T4
DataWait->AckPls	80	Covered	T1,T3,T4
DataWait->Disabled	107	Covered	T117,T17,T35
DataWait->Error	99	Covered	T14,T8,T62
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T105,T7,T102

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T1,T3,T4
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T1,T3,T4
DataWait	-	-	-	0	Covered	T1,T3,T4
AckPls	-	-	-	-	Covered	T1,T3,T4
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T5,T6,T76

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	137963	0	0
FpvSecCmErrorStEscalate_A	222469498	139002	0	0
u_state_regs_A	222435647	222270179	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	137963	0	0
T5	499	148	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	300	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	139002	0	0
T5	499	149	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	301	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222435647	222270179	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	387	244	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T28,T119
DataWait	75	Covered	T19,T28,T119
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T28,T119
DataWait->AckPls	80	Covered	T19,T28,T119
DataWait->Disabled	107	Covered	T82,T51,T68
DataWait->Error	99	Covered	T161,T31,T162
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T19,T28,T119
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T19,T28,T119
Idle	-	1	0	-	Covered	T19,T28,T119
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T19,T28,T119
DataWait	-	-	-	0	Covered	T19,T28,T119
AckPls	-	-	-	-	Covered	T19,T28,T119
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T5,T19
DataWait	75	Covered	T3,T5,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T5,T19
DataWait->AckPls	80	Covered	T3,T5,T19
DataWait->Disabled	107	Covered	T83,T163
DataWait->Error	99	Covered	T7,T58,T45
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T5,T19
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T5,T19
Idle	-	1	0	-	Covered	T3,T5,T19
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T5,T19
DataWait	-	-	-	0	Covered	T3,T19,T121
AckPls	-	-	-	-	Covered	T3,T5,T19
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T19,T120
DataWait	75	Covered	T3,T19,T120
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T19,T120
DataWait->AckPls	80	Covered	T3,T19,T120
DataWait->Disabled	107	Covered	T36,T164,T53
DataWait->Error	99	Covered	T165,T48,T166
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T19,T120
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T19,T120
Idle	-	1	0	-	Covered	T3,T19,T120
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T19,T120
DataWait	-	-	-	0	Covered	T3,T19,T120
AckPls	-	-	-	-	Covered	T3,T19,T120
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T10,T22
DataWait	75	Covered	T19,T10,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T10,T22
DataWait->AckPls	80	Covered	T19,T10,T22
DataWait->Disabled	107	Covered	T22,T167,T168
DataWait->Error	99	Covered	T96,T169,T170
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T19,T10,T22
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T19,T10,T22
Idle	-	1	0	-	Covered	T19,T10,T22
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T19,T10,T22
DataWait	-	-	-	0	Covered	T19,T10,T22
AckPls	-	-	-	-	Covered	T19,T10,T22
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T19,T55
DataWait	75	Covered	T3,T19,T55
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T95
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T19,T55
DataWait->AckPls	80	Covered	T3,T19,T55
DataWait->Disabled	107	Covered	T52,T171
DataWait->Error	99	Covered	T73
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T3,T19,T55
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T3,T19,T55
Idle	-	1	0	-	Covered	T3,T19,T55
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T3,T19,T55
DataWait	-	-	-	0	Covered	T3,T19,T55
AckPls	-	-	-	-	Covered	T3,T19,T55
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T10,T14

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T121,T122
DataWait	75	Covered	T19,T121,T122
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T3,T4
Error	99	Covered	T5,T6,T14
Idle	68	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T121,T122
DataWait->AckPls	80	Covered	T19,T121,T122
DataWait->Disabled	107	Covered	T172,T173,T174
DataWait->Error	99	Covered	T175,T89
Disabled->EndPointClear	63	Covered	T1,T3,T4
Disabled->Error	99	Covered	T6,T15,T16
EndPointClear->Disabled	107	Covered	T10,T86,T160
EndPointClear->Error	99	Covered	T6,T75,T9
EndPointClear->Idle	68	Covered	T1,T3,T4
Idle->DataWait	75	Covered	T19,T121,T122
Idle->Disabled	107	Covered	T4,T6,T20
Idle->Error	99	Covered	T5,T14,T105

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T3,T4
Idle	-	1	1	-	Covered	T19,T121,T122
Idle	-	1	0	-	Covered	T19,T121,T122
Idle	-	0	-	-	Covered	T1,T3,T4
DataWait	-	-	-	1	Covered	T19,T121,T122
DataWait	-	-	-	0	Covered	T19,T121,T122
AckPls	-	-	-	-	Covered	T19,T121,T122
Error	-	-	-	-	Covered	T5,T6,T14
default	-	-	-	-	Covered	T6,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T14
0	1	Covered	T20,T10,T14
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	222469498	140163	0	0
FpvSecCmErrorStEscalate_A	222469498	141202	0	0
u_state_regs_A	222469498	222304030	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	140163	0	0
T5	499	198	0	0
T6	45422	17190	0	0
T7	0	1092	0	0
T8	0	402	0	0
T9	0	600	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	602	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	602	0	0
T76	0	350	0	0
T102	0	602	0	0
T105	0	1113	0	0
T106	1614	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	141202	0	0
T5	499	199	0	0
T6	45422	17450	0	0
T7	0	1093	0	0
T8	0	403	0	0
T9	0	601	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	603	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	603	0	0
T76	0	351	0	0
T102	0	603	0	0
T105	0	1114	0	0
T106	1614	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0