Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T112,T113
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T115,T116
1	0	1	Covered	T3,T10,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444282818	527007	0	0
DepthKnown_A	444938996	444608060	0	0
RvalidKnown_A	444938996	444608060	0	0
WreadyKnown_A	444938996	444608060	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	444633054	603206	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444282818	527007	0	0
T3	8676	3843	0	0
T4	915030	0	0	0
T5	322	0	0	0
T6	1486	0	0	0
T7	0	67	0	0
T10	7128	4624	0	0
T11	0	1697	0	0
T14	190	0	0	0
T17	0	1874	0	0
T19	4634	0	0	0
T20	3968	0	0	0
T21	2850	0	0	0
T24	1654	0	0	0
T25	0	2894	0	0
T26	0	648	0	0
T55	0	4818	0	0
T56	0	2629	0	0
T136	0	1500	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444938996	444608060	0	0
T1	6308	6174	0	0
T2	1858	1748	0	0
T3	8676	8560	0	0
T4	915030	915004	0	0
T5	998	712	0	0
T6	90844	47668	0	0
T10	7128	6930	0	0
T19	4634	4478	0	0
T20	3968	3824	0	0
T21	2850	2726	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444938996	444608060	0	0
T1	6308	6174	0	0
T2	1858	1748	0	0
T3	8676	8560	0	0
T4	915030	915004	0	0
T5	998	712	0	0
T6	90844	47668	0	0
T10	7128	6930	0	0
T19	4634	4478	0	0
T20	3968	3824	0	0
T21	2850	2726	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444938996	444608060	0	0
T1	6308	6174	0	0
T2	1858	1748	0	0
T3	8676	8560	0	0
T4	915030	915004	0	0
T5	998	712	0	0
T6	90844	47668	0	0
T10	7128	6930	0	0
T19	4634	4478	0	0
T20	3968	3824	0	0
T21	2850	2726	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	444633054	603206	0	0
T3	8676	3843	0	0
T4	915030	0	0	0
T5	998	0	0	0
T6	1486	0	0	0
T7	0	1614	0	0
T10	7128	4624	0	0
T11	0	1697	0	0
T14	2074	238	0	0
T17	0	1874	0	0
T19	4634	0	0	0
T20	3968	0	0	0
T21	2850	0	0	0
T24	1654	0	0	0
T25	0	2894	0	0
T26	0	648	0	0
T55	0	4818	0	0
T56	0	2629	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T44,T140
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T113
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T115,T116
1	0	1	Covered	T3,T10,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222141409	258827	0	0
DepthKnown_A	222469498	222304030	0	0
RvalidKnown_A	222469498	222304030	0	0
WreadyKnown_A	222469498	222304030	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222316527	296964	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222141409	258827	0	0
T3	4338	1900	0	0
T4	457515	0	0	0
T5	161	0	0	0
T6	743	0	0	0
T7	0	23	0	0
T10	3564	2296	0	0
T11	0	816	0	0
T14	95	0	0	0
T17	0	924	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T25	0	1427	0	0
T26	0	329	0	0
T55	0	2389	0	0
T56	0	1279	0	0
T136	0	737	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222316527	296964	0	0
T3	4338	1900	0	0
T4	457515	0	0	0
T5	499	0	0	0
T6	743	0	0	0
T7	0	793	0	0
T10	3564	2296	0	0
T11	0	816	0	0
T14	1037	120	0	0
T17	0	924	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T25	0	1427	0	0
T26	0	329	0	0
T55	0	2389	0	0
T56	0	1279	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T112
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T141,T142
1	0	1	Covered	T3,T10,T14
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222141409	268180	0	0
DepthKnown_A	222469498	222304030	0	0
RvalidKnown_A	222469498	222304030	0	0
WreadyKnown_A	222469498	222304030	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222316527	306242	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222141409	268180	0	0
T3	4338	1943	0	0
T4	457515	0	0	0
T5	161	0	0	0
T6	743	0	0	0
T7	0	44	0	0
T10	3564	2328	0	0
T11	0	881	0	0
T14	95	0	0	0
T17	0	950	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T25	0	1467	0	0
T26	0	319	0	0
T55	0	2429	0	0
T56	0	1350	0	0
T136	0	763	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222316527	306242	0	0
T3	4338	1943	0	0
T4	457515	0	0	0
T5	499	0	0	0
T6	743	0	0	0
T7	0	821	0	0
T10	3564	2328	0	0
T11	0	881	0	0
T14	1037	118	0	0
T17	0	950	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T25	0	1467	0	0
T26	0	319	0	0
T55	0	2429	0	0
T56	0	1350	0	0