Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	138	1			T21	1		T27	1		T43	1
auto_req_mode	154	1			T7	1		T9	1		T19	1
sw_mode	2755	1			T1	11		T2	1		T71	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

295

1

T2

1

T7

1

T27

1

single

105

1

T21

1

T9

1

T19

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1459	1			T1	11		T7	1		T27	1
auto[2]	183	1			T39	1		T79	1		T271	1
auto[3]	121	1			T272	1		T10	1		T82	1
auto[4]	146	1			T71	1		T273	1		T274	1
auto[5]	104	1			T81	1		T275	1		T276	1
auto[6]	130	1			T86	1		T45	1		T46	1
auto[7]	904	1			T2	1		T21	1		T37	17

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	79	1			T27	1		T43	1		T73	1
auto[1]	auto_req_mode	87	1			T7	1		T9	1		T19	1
auto[1]	sw_mode	1293	1			T1	11		T38	19		T238	1
auto[2]	boot_req_mode	3	1			T277	1		T278	1		T279	1
auto[2]	auto_req_mode	4	1			T39	1		T280	1		T281	1
auto[2]	sw_mode	176	1			T79	1		T271	1		T282	61
auto[3]	boot_req_mode	6	1			T82	1		T283	1		T284	1
auto[3]	auto_req_mode	7	1			T272	1		T10	1		T11	1
auto[3]	sw_mode	108	1			T62	1		T203	56		T285	1
auto[4]	boot_req_mode	4	1			T273	1		T274	1		T286	1
auto[4]	auto_req_mode	2	1			T287	1		T288	1		-	-
auto[4]	sw_mode	140	1			T71	1		T204	50		T289	61
auto[5]	boot_req_mode	2	1			T290	1		T291	1		-	-
auto[5]	auto_req_mode	7	1			T81	1		T275	1		T276	1
auto[5]	sw_mode	95	1			T292	10		T293	1		T294	1
auto[6]	boot_req_mode	2	1			T295	1		T296	1		-	-
auto[6]	auto_req_mode	7	1			T45	1		T46	1		T297	1
auto[6]	sw_mode	121	1			T86	1		T298	1		T299	1
auto[7]	boot_req_mode	42	1			T21	1		T44	1		T84	1
auto[7]	auto_req_mode	40	1			T52	1		T48	1		T300	1
auto[7]	sw_mode	822	1			T2	1		T37	17		T72	8