Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2681	1			T1	9		T2	3		T21	2
non_zero_bins[1]	1864	1			T1	3		T7	11		T27	1
zero	8269	1			T1	29		T2	1		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	493	1			T71	1		T37	1		T38	7
uni	3514	1			T1	14		T2	1		T21	2
gen	3984	1			T1	11		T2	1		T4	1
res	871	1			T1	2		T2	1		T21	1
ins	3952	1			T1	14		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8708

1

T1

32

T2

2

T3

1

mubi_true

4106

1

T1

9

T2

2

T4

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

12814

1

T1

41

T2

4

T3

1

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	110	1			T72	1		T163	1		T84	1
upd	non_zero_bins[0]	pass	mubi_true	119	1			T38	2		T40	1		T86	1
upd	non_zero_bins[1]	pass	mubi_false	91	1			T72	1		T162	1		T245	1
upd	non_zero_bins[1]	pass	mubi_true	92	1			T38	3		T246	1		T160	2
upd	zero	pass	mubi_false	40	1			T37	1		T247	1		T82	1
upd	zero	pass	mubi_true	41	1			T71	1		T38	2		T159	1
uni	zero	pass	mubi_false	2587	1			T1	11		T2	1		T21	2
uni	zero	pass	mubi_true	927	1			T1	3		T37	8		T38	4
gen	non_zero_bins[0]	pass	mubi_false	515	1			T2	1		T7	1		T71	1
gen	non_zero_bins[0]	pass	mubi_true	528	1			T1	2		T21	1		T9	7
gen	non_zero_bins[1]	pass	mubi_false	358	1			T37	1		T38	3		T72	3
gen	non_zero_bins[1]	pass	mubi_true	342	1			T1	1		T7	11		T27	1
gen	zero	pass	mubi_false	1831	1			T1	8		T22	1		T12	1
gen	zero	pass	mubi_true	410	1			T4	1		T21	1		T8	2
res	non_zero_bins[0]	pass	mubi_false	228	1			T7	2		T27	1		T38	1
res	non_zero_bins[0]	pass	mubi_true	204	1			T1	1		T2	1		T72	1
res	non_zero_bins[1]	pass	mubi_false	145	1			T1	1		T37	1		T70	1
res	non_zero_bins[1]	pass	mubi_true	125	1			T9	2		T159	1		T78	2
res	zero	pass	mubi_false	91	1			T8	1		T38	1		T19	2
res	zero	pass	mubi_true	78	1			T21	1		T37	1		T45	2
ins	non_zero_bins[0]	pass	mubi_false	503	1			T1	4		T21	1		T71	1
ins	non_zero_bins[0]	pass	mubi_true	474	1			T1	2		T2	1		T7	1
ins	non_zero_bins[1]	pass	mubi_false	347	1			T1	1		T37	1		T38	1
ins	non_zero_bins[1]	pass	mubi_true	364	1			T9	1		T37	1		T38	2
ins	zero	pass	mubi_false	1862	1			T1	7		T3	1		T4	1
ins	zero	pass	mubi_true	402	1			T4	1		T8	1		T37	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded