Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T21
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T144,T176,T177
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T21
DataWait->AckPls	80	Covered	T1,T2,T21
DataWait->Disabled	107	Covered	T87,T91,T178
DataWait->Error	99	Covered	T3,T4,T74
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T21
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T21
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T21
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T29,T75,T76

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1334130098	999431	0	0
FpvSecCmErrorStEscalate_A	1334130098	1006732	0	0
u_state_regs_A	1334093003	1332917255	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1334130098	999431	0	0
T3	18144	8197	0	0
T4	21000	8120	0	0
T5	0	2800	0	0
T6	0	2464	0	0
T7	16002	0	0	0
T8	15701	0	0	0
T12	8946	4459	0	0
T20	10038	0	0	0
T21	21784	0	0	0
T22	15232	7742	0	0
T23	7217	0	0	0
T27	17017	0	0	0
T29	0	4080	0	0
T74	0	4305	0	0
T75	0	4318	0	0
T76	0	2659	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1334130098	1006732	0	0
T3	18144	8204	0	0
T4	21000	8127	0	0
T5	0	2807	0	0
T6	0	2471	0	0
T7	16002	0	0	0
T8	15701	0	0	0
T12	8946	4466	0	0
T20	10038	0	0	0
T21	21784	0	0	0
T22	15232	7749	0	0
T23	7217	0	0	0
T27	17017	0	0	0
T29	0	4087	0	0
T74	0	4312	0	0
T75	0	4325	0	0
T76	0	2666	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1334093003	1332917255	0	0
T1	1134924	1134826	0	0
T2	19061	18522	0	0
T3	17780	16877	0	0
T4	19783	18936	0	0
T7	16002	15463	0	0
T12	8801	8003	0	0
T20	10038	9562	0	0
T21	21784	21287	0	0
T22	15098	13894	0	0
T23	7217	6559	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T21,T7
DataWait	75	Covered	T1,T21,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T21,T7
DataWait->AckPls	80	Covered	T1,T21,T7
DataWait->Disabled	107	Covered	T178,T136,T181
DataWait->Error	99	Covered	T74,T6,T153
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T180,T13,T14
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T21,T7
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T21,T7
Idle	-	1	0	-	Covered	T1,T21,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T21,T7
DataWait	-	-	-	0	Covered	T1,T21,T7
AckPls	-	-	-	-	Covered	T1,T21,T7
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T29,T75,T76

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	140933	0	0
FpvSecCmErrorStEscalate_A	190590014	141976	0	0
u_state_regs_A	190552919	190384955	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	140933	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	540	0	0
T74	0	615	0	0
T75	0	574	0	0
T76	0	337	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	141976	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	541	0	0
T74	0	616	0	0
T75	0	575	0	0
T76	0	338	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190552919	190384955	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2228	2099	0	0
T4	1783	1662	0	0
T7	2286	2209	0	0
T12	1133	1019	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2042	1870	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T39,T40
DataWait	75	Covered	T3,T21,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T39,T40
DataWait->AckPls	80	Covered	T21,T39,T40
DataWait->Disabled	107	Covered	T182,T183
DataWait->Error	99	Covered	T3,T59,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T21,T39
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T4,T22,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T39,T40
Idle	-	1	0	-	Covered	T3,T21,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T39,T40
DataWait	-	-	-	0	Covered	T3,T21,T39
AckPls	-	-	-	-	Covered	T21,T39,T40
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T12,T41,T40
DataWait	75	Covered	T12,T41,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T12,T41,T40
DataWait->AckPls	80	Covered	T12,T41,T40
DataWait->Disabled	107	Covered	T91,T134,T184
DataWait->Error	99	Covered	T152,T118,T147
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T12,T41,T40
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T12,T41,T40
Idle	-	1	0	-	Covered	T12,T41,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T12,T41,T40
DataWait	-	-	-	0	Covered	T41,T40,T44
AckPls	-	-	-	-	Covered	T12,T41,T40
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T42,T43
DataWait	75	Covered	T21,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T42,T43
DataWait->AckPls	80	Covered	T21,T42,T43
DataWait->Disabled	107	Covered	T42,T43,T94
DataWait->Error	99	Covered	T29,T185,T105
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T21,T42,T43
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T42,T43
Idle	-	1	0	-	Covered	T21,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T42,T43
DataWait	-	-	-	0	Covered	T21,T42,T43
AckPls	-	-	-	-	Covered	T21,T42,T43
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T21,T22
DataWait	75	Covered	T2,T4,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T144,T177
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T21,T22
DataWait->AckPls	80	Covered	T2,T21,T22
DataWait->Disabled	107	Covered	T186
DataWait->Error	99	Covered	T4,T187,T96
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T4,T21
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T22,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T21,T22
Idle	-	1	0	-	Covered	T2,T4,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T21,T22
DataWait	-	-	-	0	Covered	T2,T4,T21
AckPls	-	-	-	-	Covered	T2,T21,T22
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T21,T8
DataWait	75	Covered	T2,T21,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T176
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T21,T8
DataWait->AckPls	80	Covered	T2,T21,T8
DataWait->Disabled	107	Covered	T188,T189,T190
DataWait->Error	99	Covered	T191,T103,T192
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T21,T8
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T21,T8
Idle	-	1	0	-	Covered	T2,T21,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T21,T8
DataWait	-	-	-	0	Covered	T2,T21,T42
AckPls	-	-	-	-	Covered	T2,T21,T8
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T18,T40
DataWait	75	Covered	T2,T18,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T4,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T193,T194
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T18,T40
DataWait->AckPls	80	Covered	T2,T18,T40
DataWait->Disabled	107	Covered	T87,T135,T98
DataWait->Error	99	Covered	T127,T117,T195
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T13,T14,T15
EndPointClear->Disabled	107	Covered	T72,T18,T179
EndPointClear->Error	99	Covered	T75,T180,T107
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T18,T40
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T3,T4,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T18,T40
Idle	-	1	0	-	Covered	T2,T18,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T18,T40
DataWait	-	-	-	0	Covered	T2,T18,T40
AckPls	-	-	-	-	Covered	T2,T18,T40
Error	-	-	-	-	Covered	T3,T4,T22
default	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T22
0	1	Covered	T3,T4,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	190590014	143083	0	0
FpvSecCmErrorStEscalate_A	190590014	144126	0	0
u_state_regs_A	190590014	190422050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	143083	0	0
T3	2592	1171	0	0
T4	3000	1160	0	0
T5	0	400	0	0
T6	0	352	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	637	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1106	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	590	0	0
T74	0	615	0	0
T75	0	624	0	0
T76	0	387	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	144126	0	0
T3	2592	1172	0	0
T4	3000	1161	0	0
T5	0	401	0	0
T6	0	353	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	638	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1107	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	591	0	0
T74	0	616	0	0
T75	0	625	0	0
T76	0	388	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0