Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T36
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	380466346	1085095	0	0
DepthKnown_A	381180028	380844100	0	0
RvalidKnown_A	381180028	380844100	0	0
WreadyKnown_A	381180028	380844100	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	380838792	1169378	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380466346	1085095	0	0
T3	612	228	0	0
T4	264	0	0	0
T5	0	301	0	0
T7	4572	1883	0	0
T8	4486	626	0	0
T9	0	1885	0	0
T12	582	0	0	0
T16	0	1131	0	0
T17	0	4549	0	0
T19	0	6992	0	0
T20	2868	0	0	0
T21	6224	0	0	0
T22	862	0	0	0
T23	2062	0	0	0
T27	4862	0	0	0
T42	0	4244	0	0
T70	0	3696	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381180028	380844100	0	0
T1	324264	324236	0	0
T2	5446	5292	0	0
T3	5184	4926	0	0
T4	6000	5758	0	0
T7	4572	4418	0	0
T12	2556	2328	0	0
T20	2868	2732	0	0
T21	6224	6082	0	0
T22	4352	4008	0	0
T23	2062	1874	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381180028	380844100	0	0
T1	324264	324236	0	0
T2	5446	5292	0	0
T3	5184	4926	0	0
T4	6000	5758	0	0
T7	4572	4418	0	0
T12	2556	2328	0	0
T20	2868	2732	0	0
T21	6224	6082	0	0
T22	4352	4008	0	0
T23	2062	1874	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381180028	380844100	0	0
T1	324264	324236	0	0
T2	5446	5292	0	0
T3	5184	4926	0	0
T4	6000	5758	0	0
T7	4572	4418	0	0
T12	2556	2328	0	0
T20	2868	2732	0	0
T21	6224	6082	0	0
T22	4352	4008	0	0
T23	2062	1874	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	380838792	1169378	0	0
T3	5184	2167	0	0
T4	6000	2307	0	0
T5	0	1292	0	0
T7	4572	1883	0	0
T8	4486	626	0	0
T9	0	1885	0	0
T12	2556	0	0	0
T16	0	1131	0	0
T17	0	4549	0	0
T19	0	6992	0	0
T20	2868	0	0	0
T21	6224	0	0	0
T22	4352	0	0	0
T23	2062	0	0	0
T27	4862	0	0	0
T74	0	244	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T154,T155,T156
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	190233173	548175	0	0
DepthKnown_A	190590014	190422050	0	0
RvalidKnown_A	190590014	190422050	0	0
WreadyKnown_A	190590014	190422050	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	190419396	590821	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190233173	548175	0	0
T3	306	148	0	0
T4	132	0	0	0
T5	0	203	0	0
T7	2286	970	0	0
T8	2243	310	0	0
T9	0	943	0	0
T12	291	0	0	0
T16	0	563	0	0
T17	0	2344	0	0
T19	0	3547	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	431	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T42	0	2137	0	0
T70	0	1855	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	190419396	590821	0	0
T3	2592	1132	0	0
T4	3000	1150	0	0
T5	0	756	0	0
T7	2286	970	0	0
T8	2243	310	0	0
T9	0	943	0	0
T12	1278	0	0	0
T16	0	563	0	0
T17	0	2344	0	0
T19	0	3547	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T74	0	121	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T16,T157
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T36
1	0	1	Covered	T3,T4,T7
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	190233173	536920	0	0
DepthKnown_A	190590014	190422050	0	0
RvalidKnown_A	190590014	190422050	0	0
WreadyKnown_A	190590014	190422050	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	190419396	578557	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190233173	536920	0	0
T3	306	80	0	0
T4	132	0	0	0
T5	0	98	0	0
T7	2286	913	0	0
T8	2243	316	0	0
T9	0	942	0	0
T12	291	0	0	0
T16	0	568	0	0
T17	0	2205	0	0
T19	0	3445	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	431	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T42	0	2107	0	0
T70	0	1841	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	190419396	578557	0	0
T3	2592	1035	0	0
T4	3000	1157	0	0
T5	0	536	0	0
T7	2286	913	0	0
T8	2243	316	0	0
T9	0	942	0	0
T12	1278	0	0	0
T16	0	568	0	0
T17	0	2205	0	0
T19	0	3445	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T74	0	123	0	0