Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	751809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6212411

1

T1

28

T2

54

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1830055	1			T1	273		T2	61		T3	5
values[0x0]	2373317	1			T1	11		T2	32		T3	8
values[0x1]	2760848	1			T1	14		T2	25		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	366728	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6597492

1

T1

127

T2

72

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27079	1			T1	3		T4	827		T9	3
valid_sources[0x01]	26899	1			T1	2		T4	790		T5	744
valid_sources[0x02]	26379	1			T4	851		T9	2		T5	630
valid_sources[0x03]	26721	1			T1	1		T4	836		T9	2
valid_sources[0x04]	27112	1			T4	800		T9	1		T5	691
valid_sources[0x05]	26944	1			T1	1		T4	810		T5	437
valid_sources[0x06]	25944	1			T1	1		T4	803		T5	104
valid_sources[0x07]	26637	1			T1	5		T4	851		T5	361
valid_sources[0x08]	29584	1			T1	2		T4	837		T5	326
valid_sources[0x09]	27602	1			T1	3		T4	785		T5	393
valid_sources[0x0a]	27091	1			T4	791		T5	670		T24	400
valid_sources[0x0b]	27501	1			T4	764		T5	364		T24	450
valid_sources[0x0c]	27872	1			T4	851		T9	3		T5	407
valid_sources[0x0d]	27716	1			T1	2		T4	843		T5	1132
valid_sources[0x0e]	28240	1			T4	814		T5	415		T24	463
valid_sources[0x0f]	27320	1			T1	2		T4	861		T5	660
valid_sources[0x10]	27726	1			T4	749		T9	1		T5	346
valid_sources[0x11]	27524	1			T4	798		T9	1		T5	313
valid_sources[0x12]	29090	1			T1	1		T4	830		T24	420
valid_sources[0x13]	28586	1			T4	798		T5	945		T24	457
valid_sources[0x14]	27706	1			T1	2		T4	835		T5	646
valid_sources[0x15]	27542	1			T4	762		T9	1		T5	286
valid_sources[0x16]	26795	1			T1	2		T4	803		T5	706
valid_sources[0x17]	26453	1			T4	750		T22	14		T5	500
valid_sources[0x18]	27493	1			T1	2		T4	863		T5	438
valid_sources[0x19]	27033	1			T4	846		T5	430		T24	420
valid_sources[0x1a]	28453	1			T4	815		T5	887		T24	414
valid_sources[0x1b]	27126	1			T1	5		T4	810		T9	3
valid_sources[0x1c]	27144	1			T1	1		T4	791		T5	590
valid_sources[0x1d]	26138	1			T1	1		T4	865		T5	14
valid_sources[0x1e]	26937	1			T4	862		T5	221		T24	467
valid_sources[0x1f]	25406	1			T1	3		T4	819		T5	317
valid_sources[0x20]	27148	1			T4	883		T5	421		T24	451
valid_sources[0x21]	27536	1			T1	1		T4	868		T5	156
valid_sources[0x22]	26186	1			T3	1		T4	786		T5	597
valid_sources[0x23]	25826	1			T4	864		T5	14		T24	439
valid_sources[0x24]	27088	1			T1	1		T4	877		T5	330
valid_sources[0x25]	26445	1			T4	860		T5	613		T24	437
valid_sources[0x26]	27227	1			T1	2		T4	862		T5	714
valid_sources[0x27]	27632	1			T4	840		T5	590		T23	1
valid_sources[0x28]	26789	1			T4	884		T5	850		T24	464
valid_sources[0x29]	25539	1			T1	2		T4	794		T5	691
valid_sources[0x2a]	27091	1			T4	811		T5	753		T23	2
valid_sources[0x2b]	28324	1			T1	1		T4	853		T9	2
valid_sources[0x2c]	29966	1			T1	1		T4	870		T5	311
valid_sources[0x2d]	28708	1			T1	2		T4	869		T9	1
valid_sources[0x2e]	27380	1			T1	2		T4	834		T5	1324
valid_sources[0x2f]	26952	1			T4	832		T9	2		T5	604
valid_sources[0x30]	28871	1			T4	848		T5	1343		T24	427
valid_sources[0x31]	26578	1			T4	804		T5	1		T24	446
valid_sources[0x32]	27900	1			T1	1		T4	784		T5	797
valid_sources[0x33]	27052	1			T1	1		T4	833		T5	246
valid_sources[0x34]	26249	1			T1	1		T3	1		T4	824
valid_sources[0x35]	26526	1			T4	827		T5	10		T24	440
valid_sources[0x36]	27696	1			T1	1		T4	887		T5	1110
valid_sources[0x37]	28320	1			T4	971		T5	1090		T24	472
valid_sources[0x38]	27263	1			T1	1		T4	886		T5	279
valid_sources[0x39]	27509	1			T1	4		T2	118		T4	828
valid_sources[0x3a]	28833	1			T1	1		T4	897		T9	1
valid_sources[0x3b]	28098	1			T4	853		T5	400		T23	1
valid_sources[0x3c]	28620	1			T1	4		T4	819		T5	1292
valid_sources[0x3d]	26629	1			T4	854		T9	1		T5	519
valid_sources[0x3e]	26988	1			T1	3		T4	844		T5	940
valid_sources[0x3f]	29045	1			T1	1		T4	784		T9	1
valid_sources[0x40]	26138	1			T1	3		T4	851		T5	269
valid_sources[0x41]	27109	1			T1	3		T4	830		T5	285
valid_sources[0x42]	26832	1			T1	1		T4	806		T5	376
valid_sources[0x43]	28280	1			T1	1		T4	838		T9	1
valid_sources[0x44]	27249	1			T1	2		T4	818		T9	1
valid_sources[0x45]	27446	1			T1	1		T4	764		T5	622
valid_sources[0x46]	25861	1			T1	1		T4	822		T9	1
valid_sources[0x47]	27253	1			T1	1		T3	1		T4	887
valid_sources[0x48]	25896	1			T1	1		T4	854		T9	1
valid_sources[0x49]	27657	1			T3	3		T4	839		T5	770
valid_sources[0x4a]	27653	1			T4	827		T5	481		T24	449
valid_sources[0x4b]	28123	1			T1	1		T4	813		T5	683
valid_sources[0x4c]	28136	1			T4	889		T5	375		T24	437
valid_sources[0x4d]	25811	1			T1	1		T4	880		T5	200
valid_sources[0x4e]	26983	1			T1	2		T4	828		T5	245
valid_sources[0x4f]	27693	1			T1	1		T4	805		T5	233
valid_sources[0x50]	28997	1			T1	1		T4	833		T5	781
valid_sources[0x51]	27621	1			T4	851		T9	1		T5	506
valid_sources[0x52]	26897	1			T1	1		T4	903		T5	650
valid_sources[0x53]	26987	1			T1	2		T4	856		T5	515
valid_sources[0x54]	25755	1			T1	3		T4	817		T5	554
valid_sources[0x55]	26993	1			T1	1		T4	839		T5	298
valid_sources[0x56]	26976	1			T1	2		T4	909		T5	437
valid_sources[0x57]	28012	1			T4	806		T5	586		T24	426
valid_sources[0x58]	28544	1			T4	756		T5	203		T24	431
valid_sources[0x59]	27010	1			T4	833		T9	1		T5	147
valid_sources[0x5a]	27522	1			T4	762		T9	2		T5	471
valid_sources[0x5b]	26749	1			T1	1		T4	821		T5	248
valid_sources[0x5c]	27603	1			T4	863		T9	1		T5	985
valid_sources[0x5d]	26841	1			T1	1		T4	911		T5	855
valid_sources[0x5e]	27800	1			T1	3		T4	816		T9	2
valid_sources[0x5f]	28147	1			T1	1		T4	739		T5	248
valid_sources[0x60]	25429	1			T1	1		T3	2		T4	807
valid_sources[0x61]	25285	1			T4	830		T5	281		T24	434
valid_sources[0x62]	25911	1			T1	1		T4	767		T9	1
valid_sources[0x63]	27673	1			T4	817		T9	2		T5	430
valid_sources[0x64]	28009	1			T4	864		T9	1		T5	272
valid_sources[0x65]	27973	1			T1	2		T4	879		T5	434
valid_sources[0x66]	28165	1			T4	795		T5	555		T24	465
valid_sources[0x67]	26779	1			T1	1		T4	843		T5	849
valid_sources[0x68]	25476	1			T4	727		T9	1		T5	473
valid_sources[0x69]	26881	1			T4	932		T5	144		T24	428
valid_sources[0x6a]	27584	1			T1	1		T4	872		T9	2
valid_sources[0x6b]	26818	1			T1	2		T4	792		T5	448
valid_sources[0x6c]	26122	1			T1	4		T4	886		T5	15
valid_sources[0x6d]	27830	1			T1	1		T4	850		T5	549
valid_sources[0x6e]	26348	1			T1	1		T4	857		T5	297
valid_sources[0x6f]	27195	1			T1	1		T4	816		T5	790
valid_sources[0x70]	27183	1			T1	1		T4	834		T9	1
valid_sources[0x71]	26699	1			T1	1		T4	897		T5	442
valid_sources[0x72]	26788	1			T1	2		T4	813		T9	1
valid_sources[0x73]	28064	1			T4	780		T5	926		T24	415
valid_sources[0x74]	25926	1			T4	831		T5	134		T24	503
valid_sources[0x75]	28824	1			T4	841		T5	969		T23	2
valid_sources[0x76]	28720	1			T1	1		T4	779		T9	2
valid_sources[0x77]	27913	1			T1	1		T4	832		T9	2
valid_sources[0x78]	27984	1			T1	3		T4	829		T5	444
valid_sources[0x79]	26696	1			T4	870		T9	1		T5	10
valid_sources[0x7a]	25553	1			T1	1		T4	848		T5	62
valid_sources[0x7b]	28501	1			T4	829		T9	1		T5	809
valid_sources[0x7c]	28841	1			T1	2		T4	917		T5	575
valid_sources[0x7d]	26742	1			T1	1		T4	785		T5	400
valid_sources[0x7e]	27694	1			T4	814		T5	542		T24	405
valid_sources[0x7f]	27937	1			T1	2		T4	822		T5	550
valid_sources[0x80]	28426	1			T1	1		T4	775		T5	289

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1563462

1

T1

4

T2

3

T3

3

values[0x0]

all_enables

biggest_size

2325953

1

T1

11

T2

29

T3

3

values[0x1]

all_enables

biggest_size

2322996

1

T1

13

T2

22

T3

6