Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
57.81	57.81	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	57.81	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
57.81	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	1	11	91.67
Crosses	52	26	26	50.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	1	1	50.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	26	26	50.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2716	1			T1	3		T4	21		T9	6
non_zero_bins[1]	1952	1			T2	4		T4	13		T9	1
zero	8818	1			T1	1		T2	4		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	521	1			T4	5		T5	3		T24	9
uni	3793	1			T1	1		T2	1		T4	37
gen	4101	1			T1	1		T2	4		T3	1
res	840	1			T1	1		T2	2		T4	4
ins	4231	1			T1	1		T2	1		T3	3

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9151

1

T1

2

T2

6

T3

2

mubi_true

4335

1

T1

2

T2

2

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	1	1	50.00

User Defined Bins for csrng_sts

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fail	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

pass

13486

1

T1

4

T2

8

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	26	26	50.00	26
Automatically Generated Cross Bins	52	26	26	50.00	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res , ins]	*	[fail]	*	--	--	18

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	125	1			T4	2		T5	2		T24	1
upd	non_zero_bins[0]	pass	mubi_true	109	1			T4	2		T24	3		T25	1
upd	non_zero_bins[1]	pass	mubi_false	77	1			T24	1		T57	1		T58	2
upd	non_zero_bins[1]	pass	mubi_true	94	1			T24	1		T57	1		T72	1
upd	zero	pass	mubi_false	58	1			T24	1		T57	1		T244	1
upd	zero	pass	mubi_true	58	1			T4	1		T5	1		T24	2
uni	zero	pass	mubi_false	2773	1			T1	1		T2	1		T4	25
uni	zero	pass	mubi_true	1020	1			T4	12		T5	6		T24	25
gen	non_zero_bins[0]	pass	mubi_false	552	1			T4	3		T5	2		T24	6
gen	non_zero_bins[0]	pass	mubi_true	486	1			T1	1		T4	2		T9	3
gen	non_zero_bins[1]	pass	mubi_false	400	1			T2	3		T4	1		T9	1
gen	non_zero_bins[1]	pass	mubi_true	354	1			T2	1		T4	5		T5	3
gen	zero	pass	mubi_false	1884	1			T3	1		T4	19		T5	15
gen	zero	pass	mubi_true	425	1			T4	1		T5	2		T24	8
res	non_zero_bins[0]	pass	mubi_false	197	1			T1	1		T4	1		T9	2
res	non_zero_bins[0]	pass	mubi_true	191	1			T4	2		T24	2		T57	2
res	non_zero_bins[1]	pass	mubi_false	117	1			T4	1		T5	1		T24	1
res	non_zero_bins[1]	pass	mubi_true	136	1			T24	3		T57	1		T20	2
res	zero	pass	mubi_false	107	1			T2	2		T57	1		T58	1
res	zero	pass	mubi_true	92	1			T5	2		T24	3		T57	1
ins	non_zero_bins[0]	pass	mubi_false	541	1			T4	3		T5	6		T24	10
ins	non_zero_bins[0]	pass	mubi_true	515	1			T1	1		T4	6		T9	1
ins	non_zero_bins[1]	pass	mubi_false	379	1			T4	5		T24	8		T57	6
ins	non_zero_bins[1]	pass	mubi_true	395	1			T4	1		T5	2		T24	9
ins	zero	pass	mubi_false	1941	1			T3	1		T4	19		T5	14
ins	zero	pass	mubi_true	460	1			T2	1		T3	2		T4	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded