SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 7 | 1 | T254 | 1 | T255 | 1 | T256 | 2 | ||||
others[1] | 11 | 1 | T31 | 2 | T153 | 2 | T26 | 1 | ||||
others[2] | 3 | 1 | T257 | 1 | T190 | 2 | - | - | ||||
others[3] | 15 | 1 | T27 | 1 | T253 | 2 | T135 | 2 | ||||
false | 1916 | 1 | T1 | 1 | T2 | 3 | T3 | 5 | ||||
true | 620 | 1 | T2 | 1 | T9 | 1 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T26 | 1 | T257 | 1 | T258 | 1 | ||||
others[1] | 6 | 1 | T254 | 1 | T163 | 2 | T259 | 1 | ||||
others[2] | 6 | 1 | T260 | 2 | T261 | 2 | T262 | 2 | ||||
others[3] | 14 | 1 | T87 | 2 | T27 | 1 | T28 | 1 | ||||
false | 2112 | 1 | T1 | 1 | T2 | 4 | T9 | 4 | ||||
true | 430 | 1 | T3 | 5 | T25 | 1 | T29 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 7 | 1 | T26 | 1 | T254 | 1 | T255 | 1 | ||||
others[1] | 2 | 1 | T257 | 1 | T263 | 1 | - | - | ||||
others[2] | 6 | 1 | T84 | 1 | T27 | 1 | T132 | 1 | ||||
others[3] | 9 | 1 | T10 | 1 | T28 | 1 | T131 | 1 | ||||
false | 2018 | 1 | T1 | 1 | T2 | 3 | T3 | 4 | ||||
true | 530 | 1 | T2 | 1 | T3 | 1 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 6 | 1 | T91 | 2 | T154 | 2 | T264 | 2 | ||||
others[1] | 10 | 1 | T255 | 1 | T134 | 2 | T265 | 2 | ||||
others[2] | 10 | 1 | T30 | 2 | T254 | 1 | T257 | 1 | ||||
others[3] | 9 | 1 | T26 | 1 | T28 | 1 | T259 | 1 | ||||
false | 1071 | 1 | T2 | 2 | T3 | 2 | T9 | 2 | ||||
true | 1466 | 1 | T1 | 1 | T2 | 2 | T3 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |