Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.63	100.00	94.44		81.08	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.65	100.00	94.44		81.08	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	41	3	3	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	46	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	3	3
43	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
76	1	1
77	1	1
80	1	1
81	1	1
			MISSING_ELSE
85	1	1
86	1	1
89	1	1
90	1	1
			MISSING_ELSE
94	1	1
97	1	1
98	1	1
			MISSING_ELSE
102	1	1
103	1	1
106	1	1
107	1	1
108	1	1
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
			MISSING_ELSE
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	1	1
136	1	1
137	1	1
139	1	1
144	1	1
145	1	1
146	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
171	1	1
174	1	1
182	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T30,T37
1	1	Covered	T3,T25,T29

 LINE       64
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T21,T6,T7
1	1	Covered	T2,T9,T10

 LINE       182
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T30,T31
1	0	Covered	T3,T37,T38

 LINE       184
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T10,T30,T31
1	Covered	T3,T37,T38

 LINE       184
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T10,T30,T31
1	Not Covered

 LINE       184
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T10,T30
1	Covered	T3,T37,T38

 LINE       198
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	60	81.08
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	152	Covered	T2,T9,T10
AutoCaptGenCnt	139	Covered	T2,T9,T10
AutoCaptReseedCnt	137	Covered	T2,T9,T19
AutoDispatch	121	Covered	T2,T9,T10
AutoFirstAckWait	115	Covered	T2,T9,T10
AutoLoadIns	67	Covered	T2,T9,T10
AutoSendGenCmd	146	Covered	T2,T9,T10
AutoSendReseedCmd	158	Covered	T2,T9,T19
BootDone	94	Covered	T3,T25,T29
BootGenAckWait	86	Covered	T3,T25,T29
BootInsAckWait	77	Covered	T3,T25,T29
BootLoadGen	81	Covered	T3,T25,T29
BootLoadIns	63	Covered	T3,T25,T29
BootLoadUni	98	Covered	T25,T29,T37
BootPulse	90	Covered	T3,T25,T29
BootUniAckWait	103	Covered	T25,T29,T31
Error	184	Covered	T3,T37,T38
Idle	108	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T10,T30,T31
SWPortMode	72	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	127	Covered	T2,T9,T19
AutoAckWait->Error	184	Covered	T94,T95
AutoAckWait->Idle	208	Covered	T21,T78,T96
AutoAckWait->RejectCsrngEntropy	184	Covered	T10,T30,T31
AutoCaptGenCnt->AutoSendGenCmd	146	Covered	T2,T9,T10
AutoCaptGenCnt->Error	184	Covered	T97
AutoCaptGenCnt->Idle	208	Covered	T98,T99,T100
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	158	Covered	T2,T9,T19
AutoCaptReseedCnt->Error	184	Covered	T101,T102
AutoCaptReseedCnt->Idle	208	Covered	T103,T104,T105
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	139	Covered	T2,T9,T10
AutoDispatch->AutoCaptReseedCnt	137	Covered	T2,T9,T19
AutoDispatch->Error	184	Covered	T106
AutoDispatch->Idle	134	Covered	T2,T9,T19
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	121	Covered	T2,T9,T10
AutoFirstAckWait->Error	184	Covered	T107,T108,T109
AutoFirstAckWait->Idle	208	Covered	T96,T110,T111
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	115	Covered	T2,T9,T10
AutoLoadIns->Error	184	Covered	T54,T55,T112
AutoLoadIns->Idle	208	Covered	T10,T21,T6
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	152	Covered	T2,T9,T10
AutoSendGenCmd->Error	184	Covered	T7,T113,T114
AutoSendGenCmd->Idle	208	Covered	T115,T116,T117
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	164	Covered	T2,T9,T19
AutoSendReseedCmd->Error	184	Covered	T86,T118
AutoSendReseedCmd->Idle	208	Covered	T119,T120,T121
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	98	Covered	T25,T29,T37
BootDone->Error	184	Covered	T52,T122,T123
BootDone->Idle	208	Covered	T124,T125,T126
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	90	Covered	T3,T25,T29
BootGenAckWait->Error	184	Covered	T127,T128
BootGenAckWait->Idle	208	Covered	T63,T129,T130
BootGenAckWait->RejectCsrngEntropy	184	Covered	T131,T132,T133
BootInsAckWait->BootLoadGen	81	Covered	T3,T25,T29
BootInsAckWait->Error	184	Covered	T3,T51,T125
BootInsAckWait->Idle	208	Covered	T3,T37,T38
BootInsAckWait->RejectCsrngEntropy	184	Covered	T134,T135,T136
BootLoadGen->BootGenAckWait	86	Covered	T3,T25,T29
BootLoadGen->Error	184	Covered	T137,T138
BootLoadGen->Idle	208	Covered	T43,T90,T139
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	77	Covered	T3,T25,T29
BootLoadIns->Error	184	Covered	T140
BootLoadIns->Idle	208	Covered	T141,T142,T143
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	103	Covered	T25,T29,T31
BootLoadUni->Error	184	Covered	T37,T144,T145
BootLoadUni->Idle	208	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	94	Covered	T3,T25,T29
BootPulse->Error	184	Covered	T14,T130,T146
BootPulse->Idle	208	Covered	T147,T148,T149
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Covered	T150,T151,T152
BootUniAckWait->Idle	108	Covered	T25,T29,T31
BootUniAckWait->RejectCsrngEntropy	184	Covered	T153,T87,T154
Idle->AutoLoadIns	67	Covered	T2,T9,T10
Idle->BootLoadIns	63	Covered	T3,T25,T29
Idle->Error	184	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	72	Covered	T1,T2,T4
RejectCsrngEntropy->Error	184	Covered	T15,T53,T56
RejectCsrngEntropy->Idle	208	Covered	T10,T30,T31
SWPortMode->Error	184	Covered	T75,T155,T156
SWPortMode->Idle	208	Covered	T4,T5,T24
SWPortMode->RejectCsrngEntropy	184	Covered	T15,T53,T56

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	41	2	2	100.00
CASE	60	35	35	100.00
IF	182	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if ((boot_req_mode_i && edn_enable_i))
-3-:	64	if ((auto_req_mode_i && edn_enable_i))
-4-:	68	if (edn_enable_i)
-5-:	80	if (csrng_cmd_ack_i)
-6-:	89	if (csrng_cmd_ack_i)
-7-:	97	if ((!boot_req_mode_i))
-8-:	106	if (csrng_cmd_ack_i)
-9-:	114	if (sw_cmd_req_load_i)
-10-:	120	if (csrng_cmd_ack_i)
-11-:	126	if (csrng_cmd_ack_i)
-12-:	132	if ((!auto_req_mode_i))
-13-:	136	if (max_reqs_cnt_zero_i)
-14-:	151	if (cmd_sent_i)
-15-:	163	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T29
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T29,T37
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T37,T38
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T29,T37
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T25,T29,T44
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T25,T29,T31
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T9,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T9,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T9,T19
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T19
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T9,T19
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T9,T19
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T30,T31
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T38,T6,T8

	LineNo.	Expression
-1-:	182	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	184	((state_q == Error)) ? 
-4-:	198	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T37,T38
1	0	1	-	Not Covered
1	0	0	-	Covered	T10,T30,T31
0	-	-	1	Covered	T3,T34,T10
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	237504159	149616	0	0
FpvSecCmErrorStEscalate_A	237504159	150658	0	0
u_state_regs_A	237469288	237300692	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	149616	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1099	0	0
T7	0	629	0	0
T8	0	1020	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1020	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	150658	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1100	0	0
T7	0	630	0	0
T8	0	1021	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1021	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237469288	237300692	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	973	813	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0