Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T165
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T43,T139,T166
DataWait->Error	99	Covered	T37,T38,T15
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T37,T38

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T1,T2,T4
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T37,T75,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1662529113	1063012	0	0
FpvSecCmErrorStEscalate_A	1662529113	1070306	0	0
u_state_regs_A	1662494242	1661314070	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1662529113	1063012	0	0
T3	7938	4466	0	0
T4	703514	0	0	0
T5	3821699	0	0	0
T6	0	8043	0	0
T7	0	4353	0	0
T8	0	7490	0	0
T9	33971	0	0	0
T14	0	7931	0	0
T15	0	4214	0	0
T22	7399	0	0	0
T23	12698	0	0	0
T24	3165967	0	0	0
T25	14189	0	0	0
T37	0	7776	0	0
T38	0	7490	0	0
T51	0	1813	0	0
T57	3067953	0	0	0
T58	105042	0	0	0
T75	0	4451	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1662529113	1070306	0	0
T3	7938	4473	0	0
T4	703514	0	0	0
T5	3821699	0	0	0
T6	0	8050	0	0
T7	0	4360	0	0
T8	0	7497	0	0
T9	33971	0	0	0
T14	0	7938	0	0
T15	0	4221	0	0
T22	7399	0	0	0
T23	12698	0	0	0
T24	3165967	0	0	0
T25	14189	0	0	0
T37	0	7783	0	0
T38	0	7497	0	0
T51	0	1820	0	0
T57	3067953	0	0	0
T58	105042	0	0	0
T75	0	4458	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1662494242	1661314070	0	0
T1	13405	13034	0	0
T2	31857	31360	0	0
T3	7777	6657	0	0
T4	703514	703500	0	0
T5	3821699	3821622	0	0
T9	33971	33369	0	0
T22	7399	6804	0	0
T23	12698	12012	0	0
T24	3165967	3165855	0	0
T25	14189	13685	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T4,T9
DataWait	75	Covered	T2,T4,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T4,T9
DataWait->AckPls	80	Covered	T2,T4,T9
DataWait->Disabled	107	Covered	T171,T172,T173
DataWait->Error	99	Covered	T15,T174,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T4,T9
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T38,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T4,T9
Idle	-	1	0	-	Covered	T2,T4,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T4,T9
DataWait	-	-	-	0	Covered	T2,T4,T9
AckPls	-	-	-	-	Covered	T2,T4,T9
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T37,T75,T7

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	150016	0	0
FpvSecCmErrorStEscalate_A	237504159	151058	0	0
u_state_regs_A	237469288	237300692	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	150016	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	579	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1068	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	593	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	151058	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	580	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1069	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	594	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237469288	237300692	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	973	813	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T10,T19
DataWait	75	Covered	T1,T10,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T10,T19
DataWait->AckPls	80	Covered	T1,T10,T19
DataWait->Disabled	107	Covered	T175,T176,T177
DataWait->Error	99	Covered	T37,T38,T52
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T10,T19
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T6,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T10,T19
Idle	-	1	0	-	Covered	T1,T10,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T10,T19
DataWait	-	-	-	0	Covered	T1,T10,T19
AckPls	-	-	-	-	Covered	T1,T10,T19
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T29,T42
DataWait	75	Covered	T19,T29,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T29,T42
DataWait->AckPls	80	Covered	T19,T29,T42
DataWait->Disabled	107	Covered	T139,T115,T178
DataWait->Error	99	Covered	T151,T130,T179
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T29,T42
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T37,T38

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T29,T42
Idle	-	1	0	-	Covered	T19,T29,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T29,T42
DataWait	-	-	-	0	Covered	T19,T29,T42
AckPls	-	-	-	-	Covered	T19,T29,T42
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T29,T30
DataWait	75	Covered	T1,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T29,T30
DataWait->AckPls	80	Covered	T1,T29,T30
DataWait->Disabled	107	Covered	T100,T180
DataWait->Error	99	Covered	T53,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T29,T30
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T37,T38

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T29,T30
Idle	-	1	0	-	Covered	T1,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T29,T30
DataWait	-	-	-	0	Covered	T1,T29,T42
AckPls	-	-	-	-	Covered	T1,T29,T30
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T29,T42
DataWait	75	Covered	T1,T3,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T29,T42
DataWait->AckPls	80	Covered	T1,T29,T42
DataWait->Disabled	107	Covered	T99,T181,T182
DataWait->Error	99	Covered	T3,T107,T183
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T29
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T37,T38,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T29,T42
Idle	-	1	0	-	Covered	T1,T3,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T29,T42
DataWait	-	-	-	0	Covered	T1,T3,T29
AckPls	-	-	-	-	Covered	T1,T29,T42
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T21,T42
DataWait	75	Covered	T29,T21,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T29,T21,T42
DataWait->AckPls	80	Covered	T29,T21,T42
DataWait->Disabled	107	Covered	T129,T98,T184
DataWait->Error	99	Covered	T185,T186,T123
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T29,T21,T42
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T37,T38

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T29,T21,T42
Idle	-	1	0	-	Covered	T29,T21,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T29,T21,T42
DataWait	-	-	-	0	Covered	T29,T21,T42
AckPls	-	-	-	-	Covered	T29,T21,T42
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T34,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T29,T43
DataWait	75	Covered	T1,T29,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T37,T38
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T165
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T29,T43
DataWait->AckPls	80	Covered	T1,T29,T43
DataWait->Disabled	107	Covered	T43,T166,T63
DataWait->Error	99	Covered	T14,T55,T187
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T167,T168,T169
EndPointClear->Error	99	Covered	T8,T170,T16
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T29,T43
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T3,T37,T38

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T29,T43
Idle	-	1	0	-	Covered	T1,T29,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T29,T43
DataWait	-	-	-	0	Covered	T1,T29,T43
AckPls	-	-	-	-	Covered	T1,T29,T43
Error	-	-	-	-	Covered	T3,T37,T38
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T34,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	237504159	152166	0	0
FpvSecCmErrorStEscalate_A	237504159	153208	0	0
u_state_regs_A	237504159	237335563	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	152166	0	0
T3	1134	638	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1149	0	0
T7	0	629	0	0
T8	0	1070	0	0
T9	4853	0	0	0
T14	0	1133	0	0
T15	0	602	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1118	0	0
T38	0	1070	0	0
T51	0	259	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	643	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	153208	0	0
T3	1134	639	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1150	0	0
T7	0	630	0	0
T8	0	1071	0	0
T9	4853	0	0	0
T14	0	1134	0	0
T15	0	603	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T37	0	1119	0	0
T38	0	1071	0	0
T51	0	260	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	644	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0