Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T33,T39
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40,T41
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	474290032	534292	0	0
DepthKnown_A	475008318	474671126	0	0
RvalidKnown_A	475008318	474671126	0	0
WreadyKnown_A	475008318	474671126	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	474658488	620787	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474290032	534292	0	0
T2	9102	6351	0	0
T3	186	0	0	0
T4	201004	0	0	0
T5	1091914	0	0	0
T6	0	220	0	0
T9	9706	4480	0	0
T10	0	776	0	0
T19	0	1250	0	0
T20	0	6086	0	0
T21	0	3282	0	0
T22	2114	0	0	0
T23	3628	0	0	0
T24	904562	0	0	0
T25	4054	0	0	0
T30	0	765	0	0
T31	0	616	0	0
T57	876558	0	0	0
T157	0	8428	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475008318	474671126	0	0
T1	3830	3724	0	0
T2	9102	8960	0	0
T3	2268	1948	0	0
T4	201004	201000	0	0
T5	1091914	1091892	0	0
T9	9706	9534	0	0
T22	2114	1944	0	0
T23	3628	3432	0	0
T24	904562	904530	0	0
T25	4054	3910	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475008318	474671126	0	0
T1	3830	3724	0	0
T2	9102	8960	0	0
T3	2268	1948	0	0
T4	201004	201000	0	0
T5	1091914	1091892	0	0
T9	9706	9534	0	0
T22	2114	1944	0	0
T23	3628	3432	0	0
T24	904562	904530	0	0
T25	4054	3910	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475008318	474671126	0	0
T1	3830	3724	0	0
T2	9102	8960	0	0
T3	2268	1948	0	0
T4	201004	201000	0	0
T5	1091914	1091892	0	0
T9	9706	9534	0	0
T22	2114	1944	0	0
T23	3628	3432	0	0
T24	904562	904530	0	0
T25	4054	3910	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	474658488	620787	0	0
T2	9102	6351	0	0
T3	2268	254	0	0
T4	201004	0	0	0
T5	1091914	0	0	0
T9	9706	4480	0	0
T10	0	776	0	0
T19	0	1250	0	0
T20	0	6086	0	0
T21	0	3282	0	0
T22	2114	0	0	0
T23	3628	0	0	0
T24	904562	0	0	0
T25	4054	0	0	0
T30	0	765	0	0
T37	0	314	0	0
T38	0	292	0	0
T57	876558	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T154
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T33
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T41
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T19

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	237145016	261925	0	0
DepthKnown_A	237504159	237335563	0	0
RvalidKnown_A	237504159	237335563	0	0
WreadyKnown_A	237504159	237335563	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	237329244	304982	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237145016	261925	0	0
T2	4551	3162	0	0
T3	93	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	61	0	0
T9	4853	2197	0	0
T10	0	386	0	0
T19	0	614	0	0
T20	0	3039	0	0
T21	0	1560	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T30	0	384	0	0
T31	0	314	0	0
T57	438279	0	0	0
T157	0	4200	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	237329244	304982	0	0
T2	4551	3162	0	0
T3	1134	131	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	2197	0	0
T10	0	386	0	0
T19	0	614	0	0
T20	0	3039	0	0
T21	0	1560	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T30	0	384	0	0
T37	0	161	0	0
T38	0	147	0	0
T57	438279	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T39,T158,T159
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T40
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	237145016	272367	0	0
DepthKnown_A	237504159	237335563	0	0
RvalidKnown_A	237504159	237335563	0	0
WreadyKnown_A	237504159	237335563	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	237329244	315805	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237145016	272367	0	0
T2	4551	3189	0	0
T3	93	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	159	0	0
T9	4853	2283	0	0
T10	0	390	0	0
T19	0	636	0	0
T20	0	3047	0	0
T21	0	1722	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T30	0	381	0	0
T31	0	302	0	0
T57	438279	0	0	0
T157	0	4228	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	237329244	315805	0	0
T2	4551	3189	0	0
T3	1134	123	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	2283	0	0
T10	0	390	0	0
T19	0	636	0	0
T20	0	3047	0	0
T21	0	1722	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T30	0	381	0	0
T37	0	153	0	0
T38	0	145	0	0
T57	438279	0	0	0